Datasheet > AN734

AN734

更新时间： 2022-11-26 13:53:59

品牌	Logo	应用领域
威世 - VISHAY		稳压器
页数	文件大小	规格书
5页	50K
描述
Design Guidelines for the Low-Noise Low-Dropout Regulator Si9181

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AN734 数据手册

AN734

Vishay Siliconix

DYNAMIC LOAD RESPONSE

PCB LAYOUT

The ability to use a low ESR ceramic capacitor at the output of

the Si9181 helps reduce the glitch during the high slew-rate

step load, while the high closed loop bandwidth reduces the re-

covery time. With a 2.2-mF ceramic capacitor at the output, the

maximum deviation observed in the output is 30 mV, with bet-

ter than 3-mS recovery time. Refer to the Figures 5 and 6. The

recovery time of the output from overshoot during the load re-

moval is the time required to discharge the output capacitor.

The recovery time depends on the voltage overshoot, capaci-

tor and the load current.

The component placement around the LDO should be done

carefully to achieve good dynamic line and load response. The

input and noise capacitor should be kept close to the LDO. The

rise in junction temperature depends on how efficiently the

heat is carried away from the junction to ambient. The junction

to lead thermal impedance is a characteristic of the package

and is fixed. The thermal impedance between lead to ambient

can be reduced by increasing the copper area on PCB. In-

crease the input, output and ground trace area to reduce the

junction-to-ambient thermal impedance.

OUT

10 mV/div

LOAD

100 mA/div

5.00 ms/div

= 3.3 V

OUT

= 2.2mF

= 2.2 mF

= 1 to 150 mA

= 2 msec

OUT

LOAD

rise

Figure 5. Load Transient Response-1

OUT

10 mV/div

LOAD

100 mA/div

5.00 ms/div

= 3.3 V

OUT

= 2.2mF

= 2.2 mF

= 150 to 1 mA

= 2 msec

OUT

LOAD

fall

Figure 6. Load Transient Response-2

Document Number: 71337

31-Oct-00

www.vishay.com

1 2 3 45

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