AN734
Vishay Siliconix
60
40
20
180
120
60
Phase
2V/div
2V/div
Gain
0
–20
–40
–60
0
2V/div
2V/div
–60
–120
–180
CH1 – V
(Pin 5)
OUT
100
1000
10000
100000
1000000
CH2 – Error (Pin 7)
CH3 – V (Pin 4)
Frequency (Hz)
IN
CH4 – C
(Pin 2)
DELAY
C
IN
= 2.2 mF, C
= 2.2 mF, I
= 150 mA
OUT
LOAD
C
DELAY
= 0.1mF
FIGURE 4. Closed Loop Bandwidth
FIGURE 5. Programmed Delay for Error
Signal
lator operation. This allows the Si9181 to be used as a high-
current simple disconnect switch that works in conjunction with
the regulated output. It is recommended that the user connect
the SD to the input VIN when not in use.
ERROR SIGNAL WITH PROGRAMMABLE DELAY
The Si9181 is provided with an ERROR pin which can be used
as a high-going enable or power-good signal to activate the
electronic equipment once the output is within 5% of the set
value. When output voltage drops below 95% of its set level,
the ERROR pin can positively disable the electronics before
the low-going supply cripples the circuit. The ERROR signal
required to wake up the electronics can also be delayed with
respect to the output by adding a small capacitor at CDELAY
(pin 2). The ERROR output is a high slew–rate open drain and
needs an external pull-up resistor.
INPUT/OUTPUT CAPACITOR SELECTION
The circuit stability and output voltage during line and load step
changes dominate the selection criteria of input and output ca-
pacitors. A higher step load current at the output demands
higher capacitance with a lower ESR value at the output. An
input bypass capacitor is required in applications involving
long traces between the source and LDO. The input capacitor
should be at least equal to or greater than the output capacitor
for proper operation. A 2.2-mF to 10-mF ceramic capacitor with
a Y5V dielectric is recommended, and an X5R dielectric is rec-
ommended for better temperature characteristics. The Si9181
requires only a small output capacitor because of the high
closed loop bandwidth of 100 kHz or more. Also, the freedom
to use a very low–ESR ceramic capacitor reduces the form
The CDELAY capacitor is fully discharged through U2 when the
circuit is OFF or when the output is below the set power-good
threshold (0.95 VOUT). (See Figure 1.) Once the output goes
above the power-good trip threshold, the U2 output switches to
a high impedance state and CDELAY charges with a 2.2-mA
(typ) constant current. U3 switches Q2 off at 1.215 V across
the CDELAY capacitor and the ERROR output is pulled high by
REXT (Figure 5).
factor further for greater performance.
+
1.81 10*6 tDELAY
(7)
CDELAY
ISTEP t
RESPONSE ) ISTEP ESR
(8)
DV +
COUT
SHUTDOWN
The Si9181 is provided with an ON/OFF control pin (named
SD) that opens and closes the internal power MOSFET switch
and controls the total current drawn by the entire circuit. The
current is less than 1 mA, reducing the drain on the battery in
standby mode and increasing standby time. While a low at the
SD pin opens the switch, a high at the SD pin enables the regu-
where:
STEP = Output load step (A)
I
ESR = ESR of Output capacitor (W)
tRESPONSE = Response time of the regulator (s)
tRESPONSE depends on the unity gain bandwidth and the phase
margin of the closed loop.
Document Number: 71337
31-Oct-00
www.vishay.com
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