AMMP-6430 Application and Usage
Recommended quiescent DC bias condition for optimum
power and linearity performances is Vd=5 volts with Vg
(-1.1V) set for Id=650 mA. Minor improvements in per-
formance are possible depending on the application.
The drain bias voltage range is 3 to 5V. A single DC gate
supply connected to Vg will bias all gain stages. Muting
can be accomplished by setting Vg to the pinch-off
voltage Vp.
emerging from the RF output port. The detected voltage
is given by :
V = Vref −Vdet −Vofs
where V is the voltage at the DET_R port, V is a
ref
det
voltage at the DET_0 port, V and is the zero-input-
ofs
power offset voltage.
A simplified schematic for the AMMP6430 MMIC die
is shown in Figure 12. The MMIC die contains ESD and
over voltage protection diodes for Vg, and Vd terminals.
The package diagram for the recommended assembly
is shown in Figure 13. In finalized package form, ESD
diodes protect all possible ESD or over voltage damages
between Vgg and ground, Vgg and Vdd, Vdd and ground.
Typical ESD diode current versus diode voltage for 11-
connected diodes in series is shown in Figure 14. Under
the recommended DC quiescent biasing condition at
Vds=5V, Ids=650mA, Vgg=-1V, typical gate terminal
current is approximately 0.3mA. If an active biasing
technique is selected for the AMMP6430 MMIC PA DC
biasing, the active biasing circuit must have more than
10-times higher internal current that the gate terminal
current.
There are three methods to calculate V
:
ofs
1. V
can be measured before each detector
ofs
measurement (by removing or switching off the
power source and measuring V - V ). This method
ref
det
gives an error due to temperature drift of less than
0.01dB/50°C.
2. V
can be measured at
a
single reference
ofs
temperature. The drift error will be less than 0.25dB.
3. V can either be characterized over temperature and
ofs
stored in a lookup table, or it can be measured at two
temperatures and a linear fit used to calculate V at
any temperature. This method gives an error close to
the method #1.
ofs
The RF ports are AC coupled at the RF input to the first
stage and the RF output of the final stage. No ground
wired are needed since ground connections are made
with plated through-holes to the backside of the device.
An optional output power detector network is also
provided. The differential voltage between the Det-Ref
and Det-Out pads can be correlated with the RF power
DET_R
Vd
Vg
DQ
DET_O
RFout
RFin
Three stage 0.5W power amplifier
Figure 12. Simplified schematic for the MMIC die
6