AMIS−30585
DETAILED BLOCKS DESCRIPTION
optimized for IO handling. For most of the instructions, the
machine is able to perform one instruction per clock cycle.
The microcontroller contains the necessary hardware to
implement interrupt mechanisms, timers and is able to
perform byte multiplication over one instruction cycle. The
microcontroller is programmed to handle the physical layer
(chip synchronization), the MAC. The program is stored in
a masked ROM. The RAM contains the necessary space to
store the working data. The back−end interface is done
through the SPI block. This back−end is used for data
transmission with the application hardware (concentrator,
power meter, etc.) and for the definition of the modem
configuration.
Receiver Path Description
The analog signal coming from the line−interface chip is
low pass filtered in order to avoid aliasing during the
conversion. Then the level of the signal is automatically
adapted by an automatic gain control (AGC) block. This
operation maximizes the dynamic range of the incoming
signal. The signal is then converted to its digital
representation using sigma delta modulation. From then on,
the processing of the data is done in a digital way. By using
dedicated hardware, a direct quadrature demodulation is
performed. The signal demodulated in the base band is then
low pass filtered to reduce the nose and reject the image
spectrum.
Clock and Control
According to the IEC standard, the frame data is
transmitted at the zero crossing of the mains voltage. In
order to recover the information at the zero crossing, a zero
Transmitter Path Description
For the generation of the tones, the direct digital synthesis
of the sine wave frequencies is performed under the control
of the microprocessor. After a signal conditioning step, a
digital to analog conversion is performed. As for the receive
path, a sigma delta modulation technique is used. In the
analog domain, the signal is low pass filtered, in order to
remove the high frequency quantization noise, and passed to
the automatic level controller (ACL) block, where the level
of the transmitted signal can be adjusted. The determination
of the signal level is done through the sense circuitry.
crossing detection of the mains is performed.
A
phase−locked loop (PLL) structure is used in order to allow
a more reliable reconstruction of the synchronization. This
PLL permits as well a safer implementation of the
“repetition with credit” function (also known as chorus
transmission). The clock generator makes use of a precise
quartz oscillator master. The clock signals are then obtained
by the use of a programmed division scheme. The support
circuits are also contained in this block. The support circuits
include the necessary blocks to supply the references
voltages for the AD and DA converters, the biasing currents
and power supply sense cells to generate the right power off
and startup conditions.
Communication Controller
The communication channel is controlled by an
embedded microcontroller. The processor uses the ARM
reduced instruction set computer (RISC) architecture
1
28
M50HZ_IN
IO0
TX_ENB
TEST
RESB
IO1
TDO
TDI
TCK
BR0
TMS
BR1
TRSTB
IO2
Figure 2. Pin−out of AMIS−30585
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