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AMIS-710600-A8

更新时间： 2024-01-16 04:15:49

品牌	Logo	应用领域
AMI		传感器换能器图像传感器
页数	文件大小	规格书
7页	291K
描述
600dpi CIS Module

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AMIS-710600-A8 技术参数

生命周期：	Transferred	Reach Compliance Code：	compliant
风险等级：	5.76	Base Number Matches：	1

AMIS-710600-A8 数据手册

AMIS-710600-A8: 600dpi CIS Module

Data Sheet

5.0 Timing Characteristics of the Module (25°C)

The input control clocks and video pixel output relationships are depicted in Figure 3. As indicated, the internal shift register is loaded

on the falling edges of the module's clock, CP and during this time the SP is high or true. To ensure that only one shift register pulse is

loaded into the shift register during any one line scan, only one SP is allowed to go high for one CP cycle going low. After loading the

shift register, the SP is to remain low throughout the remainder of the line scan; otherwise multiple start pulses will load into the shift

register. To prevent this phenomenon, as the timing diagram shows, SP should occur only once in one CP cycle. When only one pulse

is loaded in the register, a single pulse shifts down the register, accessing a single photo-site with each shift and sequentially reading it

out onto the common video line where the video pixel is amplified and produced at the output I/O.

Figure 3: Timing Diagram of SP Relative to First Pixel

The call outs for the switching characteristics in Figure 3 are given in Table 6. This table defines the symbols used in the timing diagram

and calls out their time durations.

Table 6: Timing Definition and Specifications

Item

Symbol

Min.

290

120

Typ.

Max.

7440

Units

Clock cycle time

Clock pulse width

Clock duty cycle

Prohibit crossing time of SP

Data setup time

Data hold time

Signal delay time

Signal sample and hold time

tprh

tds

tdh

tdl

tsh

AMI Semiconductor – July. 06, M-20597-001

www.amis.com

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