Datasheet > AM29LV008B-120EC

AM29LV008B-120EC

更新时间： 2024-02-22 02:46:56

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
39页	142K
描述
Flash, 1MX8, 120ns, PDSO40, TSOP-40

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技术参数
数据手册

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AM29LV008B-120EC 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.74
Base Number Matches：	1

AM29LV008B-120EC 数据手册

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P R E L I M I N A R Y

USER BUS OPERATIONS

Read Mode

Deselecting CE (CE and RESET = V

± 0.3 V) puts

the device into the I

standby mode. If the device is

CC3

The Am29LV008 has three control functions which

must be satisﬁed in order to obtain data at the outputs:

deselected during an Embedded Algorithm operation,

it continues to draw active power (I ) prior to entering

CC2

■ CE is the power control and should be used for de-

the standby mode, until the operation is complete.

vice selection (CE = V )

When the device is again selected (CE = V ), active

operations occur in accordance with the AC timing

speciﬁcations.

■ OE is the output control and should be used to gate

data to the output pins if the device is selected

(OE = V )

Automatic Sleep Mode

■ WE remains at V

Advanced power management features such as the

automatic sleep mode minimize Flash device energy

consumption. This is extremely important in

battery-powered applications. The Am29LV008 auto-

matically enables the low-power, automatic sleep

mode when addresses remain stable for 200 ns. Auto-

matic sleep mode is independent of the CE, WE, and

OE control signals. Typical sleep mode current draw is

200 nA (for CMOS-compatible operation). Standard

address access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

Address access time (T

stable addresses to valid output data. The chip enable

) is equal to the delay from

ACC

access time (T ) is the delay from stable addresses

and stable CE to valid data at the output pins. The out-

put enable access time (T ) is the delay from the fall-

ing edge of OE to valid data at the output pins

(assuming the addresses have been stable at least

– T time).

ACC

Standby Mode

The Am29LV008 is designed to accommodate low

standby power consumption by applying the following

voltages to the CE and RESET pins: I

compatible I/Os (current consumption <5 µA max.) is

enabled when a CMOS logic level ‘1’ (V ± 0.3 V) is

applied to the CE control pin with RESET = V ± 0.3

Output Disable

for CMOS

CC3

If the OE input is at a logic high level (V ), output from

the device is disabled.This will cause the output pins to

be in a high impedance state.

V.While in the I

standby mode, the data I/O pins re-

CC3

main in the high impedance state independent of the

voltage level applied to the OE input. See the DC Char-

acteristics section for more details on Standby Modes.

Am29LV008T/Am29LV008B

1...5 6 789 10 11...39

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