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AL4V185 PDF预览

AL4V185

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
凌泰科技 - AVERLOGIC 先进先出芯片
页数 文件大小 规格书
2页 31K
描述
16K, 64K-Bit Line FIFO

AL4V185 数据手册

 浏览型号AL4V185的Datasheet PDF文件第1页 
/OE  
(1k , 4k) x18  
Memory  
Array  
Input  
Buffer  
Output  
Buffer  
Input data bus  
Output data bus  
WCLK  
/WEN  
Write  
Control  
Logic  
Read  
Control  
Logic  
RCLK  
/REN  
Write Pointer  
Read Pointer  
/RRSTB  
/WRSTB  
/BEB  
/IW  
/OW  
Offset  
Regissers  
Timing &  
Control Logic  
Figure 1. AL4V18x FIFO Block Diagram  
output data bus width by packing or unpacking  
the data. A Big-Endian/Little-Endian data word  
format is provided to invert the read-in bytes  
sequence for output. And the Retransmit function  
allows data to be reread from the FIFO more than  
once.  
The 18bit input and output ports operate  
independently at a maximum speed of 100 MHz.  
The built-in address decoder and pointer  
managing circuits provide a straightforward bus  
interface to serially read/write memory that  
reduces inter-chip design efforts. The AL4V18x  
embedded memory array and high performance  
process technologies with extended controller  
functions (read skip, fixed and programmable  
status flags... etc.) offer flexible memory  
management.  
These chips are available as a 64pin STQFP  
Package.  
These FIFOs support up to 18-bit input and output  
data bus-width that is controlled by separate clock  
and enable signals respectively. The input data is  
acquired at each rising edge of a free running  
write clock while a write enable control pin is  
asserted. The output data is available after each  
rising edge of a free running read clock while a  
read enable and output enable control pins are  
asserted. When output enable (/OE) is LOW, the  
data output bus is active. If /OE is HIGH, the  
output data bus will be in a high-impedance. This  
signal can control whether the data is going to be  
skipped during the read operation.  
DISTRIBUTED BY:  
Bus-Matching feature can flexibly configure input  
and output bus width. The chip can automatically  
convert the input data bus width to match up  
A
VER  
L
OGIC  
OGIC  
T
T
ECHNOLOGIES, INC  
ECHNOLOGIES, CORP  
.
TEL: 1 408 361-0400  
e-mail: sales_usa@averlogic.comURL: www.averlogic.com  
AVER  
L
.
TEL: 886 2-87523988 e-mail: sales@averlogic.com.tw URL: www.averlogic.com.tw  
October 30, 2004  

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