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AK8181H PDF预览

AK8181H

更新时间: 2024-01-24 02:16:31
品牌 Logo 应用领域
AKM 时钟
页数 文件大小 规格书
12页 542K
描述
2.5V, 3.3V LVPECL 1:10 Clock Fanout Buffer

AK8181H 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LQFP, QFP32,.35SQ,32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.75
系列:8181输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.375/3.8 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:700 MHzBase Number Matches:1

AK8181H 数据手册

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AK8181H  
AC Characteristics  
All specifications at VDD = 2.375V to 3.8V or, VSS = 0V, Ta: -40 to +85, unless otherwise noted  
Parameter  
Output Frequency  
Propagation Delay (1)  
Output Skew (2) (3)  
Part-to-Part Skew (3) (4)  
Buffer Additive Jitter, RMS (5)  
Output Rise/Fall Time (5)  
Output Duty Cycle  
Symbol  
Conditions  
MIN  
TYP  
MAX  
700  
Unit  
MHz  
ns  
fOUT  
tPD  
T.B.D  
tsk(O)  
tskPP  
tjit  
30  
0.045  
50  
ps  
340  
ps  
155.52MHz (12kHz 20MHz)  
ps  
tr, tf  
DCOUT  
20% to 80%  
150  
47  
500  
53  
ps  
%
All parameters measured at f 700MHz unless noted otherwise.  
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.  
(1) Measured from the differential input crossing point to the differential output crossing point.  
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output  
differential cross points.  
(3) This parameter is defined in accordance with JEDEC Standard 65.  
(4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load  
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.  
(5) Design value.  
Feb-2013  
draft-E-02  
- 6 -  

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