[AK7719B]
4. Block Diagram
■ Block Diagram
VSS
TVDD
VDD
PDN
TEST
Port#2/5
Slave
SYNC5
Port#1
Slave
BCLK5
UPDN
Conv
SYNC
SYNC1
SDOUT5
SDIN5
SYNC
BCLK
BCLK
DIN2
BCLK1
SDIN1
SRCAO
SRCAI
DOUT1
SYNC2
DIN1
SDOUT1
DOUT2
BCLK2
SDOUT2
SDIN2
SDOUT4/
GP1/STO/
RDY
DOUT4/GP1
WDT/CRC
SELSRC bit = “0”
SYNC
BCLK
(Port#3)
PCM Interface4
(Port#4)
Slave
Through
DOUT3/GP0
DIN3
SDOUT3/GP0
SDIN3
SYNC4
SYNC3/JX1
BCLK3/JX0
JX1
JX0
SYNC
BCLK
BCLK4
SDIN4
DIN4
SRCBI
AKM
DSP
I2C
SCLK/CAD0
SI/CAD1
Core
Control
Interface
CGU
(CLK
Gen
DSPCLK
CSN/SCL
SO/SDA
Memory
Unit)
Figure 1. Block Diagram (SELSRC bit = “0”)
VSS
TVDD
VDD
PDN
TEST
Port#2/5
SYNC5
BCLK5
Port#1
UPDN
Conv
SYNC1
BCLK1
SYNC
SDOUT5
SDIN5
SYNC
BCLK
BCLK
DIN2
DOUT1
SDIN1
Through
SYNC2
DIN1
SDOUT1
DOUT2
BCLK2
SDOUT4/
GP1/STO/
RDY
DOUT4/GP1
WDT/CRC
SDOUT2
SELSRC bit = “1”
SDIN2
Port#3
Port#4
SYNC3/JX1
SYNC4
SYNC
BCLK
BCLK3/JX0
SYNC
BCLK
BCLK4
SDIN4
SRCAO
SRCAI
DOUT3/GP0
DIN3
SDOUT3/GP0
DIN4
SRCBI
SDIN3
AKM
DSP
Core
I2C
SCLK/CAD0
SI/CAD1
Control
Interface
CGU
(CLK
Gen
DSPCLK
Memory
CSN/SCL
SO/SDA
Unit)
Figure 2. Block Diagram (SELSRC bit = “1”)
MS1565-E-00-PB
2013/11
3