Accutek
Microcircuit
Corporation
AK632256W / AK632256Z
262,144 x 32 Bit CMOS/BiCMOS
Static Random Access Memory
DESCRIPTION
Front View
64-Pin SIM
The Accutek AK632256 SRAM Module consists of eight fast high
performance SRAMs mounted on a low profile, 64 pin SIM or ZIP
Board. The module utilizes four 28 pin 256K x 4 SRAMs in SOJ
packages and four decoupling capacitors mounted on each side of
a printed circuit board.
1
32 33
64
The SRAMs used have common I/O functions and single output en-
able functions. Also, four separate chip select (CE) connections are
used to independently enable the four bytes. The modules can be
supplied in a variety of access time values from 12 nSEC to
45 nSEC in CMOS or BiCMOS technology.
64-Pin ZIP
The Accutek module is designed to have a maximum seated height
of 0.680 inch SIM or 0.540 inch ZIP to provide for the lowest height
off the board. By offset-mounting the back surface SRAMs on the
SIM version, the module can be mounted in either angled or
straight-up SIM sockets. Each conforms to JEDEC standard sizes
and pin-out configurations. Using two pins for module memory den-
sity identification, PD0 and PD1, minimizes interchangeability and
design considerations when changing from one module size to an-
other in customer applications.
1
32
33
64
· Downward compatible with 32K x 32 (AK63232), 64K x 32
(AK63264) and 128K x 32 (AK632128)
· Presence Detect PD0 and PD1 for identifying module density
· Fast access times range from 12 nSEC BiCMOS to 45 nSEC
CMOS
· TTL-compatible inputs and outputs
· Single +5 Volt ( 10ꢀ) power supply
· Operating temperature range in free air, 00C to 700C
FEATURES
· 262,144 x 32 bit organization
ELECTRICAL SPECIFICATIONS
· JEDEC Standardized 64 pin SIM or ZIP format
Timing diagrams and basic electrical characteristics are those of
the standard 256K x 4 SRAMs used to construct these modules.
Accutek’s module design allows the flexibility of selecting indus-
try-compatible 256K x 4 SRAMs from several semiconductor manu-
facturers.
· Common I/O, single OE functions with four separate chip
selects (CE)
· Low height, 0.680 inch SIM or 0.540 inch ZIP maximum
· Upward compatible with 512K x 32 (AK532512) and
1 Meg x 32 (AK6321024)
PIN NOMENCLATURE
PIN ASSIGNMENT
FUNCTIONAL DIAGRAM
PIN #
1
SYMBOL
Vss
PD0
PD1
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ4
DQ12
Vcc
A0
PIN #
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SYMBOL
A2
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SYMBOL
CE4
CE3
A17
PIN #
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SYMBOL
A4
A0 - A17
CE1 - CE4
DQ1 - DQ32
OE
Address Inputs
Chip Enable
Data In/Data Out
Output Enable
Presence Detect
5v Supply
2
A9
A11
3
DQ13
DQ5
DQ14
DQ6
DQ15
DQ7
DQ16
DQ8
Vss
WE
A5
4
A16
A12
5
OE
Vcc
PD0 - PD1
Vcc
6
Vss
A13
7
DQ25
DQ17
DQ26
DQ18
DQ27
DQ19
DQ28
DQ20
A3
A6
8
DQ21
DQ29
DQ22
DQ30
DQ23
DQ31
DQ24
DQ32
Vss
Vss
Ground
9
WE
Write Enable
10
11
12
13
14
15
16
MODULE OPTIONS
A15
A7
A14
Leadless SIM: AK632256W
Leaded SIP: AK632256G
Leaded ZIP: AK632256Z
A1
CE2
CE1
A8
A10
PD0 = Vss
PD1 = Vss
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