Datasheet > AI5412

AI5412

更新时间： 2022-12-17 01:08:22

品牌	Logo	应用领域
A1PROS		控制器摄像机
页数	文件大小	规格书
20页	224K
描述
Timing Controller for CCD Monochrome Camera

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中文翻译

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数据手册

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AI5412 数据手册

Ai5412

External Synchronization

1) External/internal sync selection

External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL

and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations.

VR/SYNC pin : SYNC signal VR/SYNC pin : VD signal

VR/SYNC pin : Open

Input

pattern

HPLL pin

: Open

HPLL pin

: HD signal

HPLL pin

: Open

ESYNC pin : Open

ESYNC pin : V_DD

ESYNC pin : Open

EXT pin

output

High

Low

Sync state

External sync

Internal sync

Note ) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal.

The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as

the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator

for improving the oscillation accuracy for internal synchronization.

2) Modes for external synchronization

Mode

Field accumulation

Frame accumulation

Interlace

SYNC

synchronization

Non-interlace

Interlace

(Cannot be accomplished since

interlace operation is the prior condition)

(Cannot be accomplished since

interlace operation is the prior condition)

VD/HD

synchronization

Non-interlace

(Not practically applicable since

the sensitivity is halved)

3) Reset operation

SYNC synchronization

The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA,V reset is

performed so that the VD pulse falls at the count of 259H (262.5-3.5H) from the fall of the VR1 pulse. For

CCIR, it is reset in such a way that the VD pulse falls at the count of 309H(312.5-3.5H).For these

reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard.

VD/HD synchronization

V reset is performed so that the VD pulse 1H later after detecting the fall of the VD(VDR) pulse supplied

externally. Therefore, this enables V reset operation regardless of the field line number. The phase

difference between the VDRpulse and HD pulse which is locked horizontally at PLL circuit identifies

whether the field is odd or even.

(VDR must have a pulse width of 2H or more.)

1...4 5 678 9 10...20

中文翻译

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与AI5412相关器件

型号	品牌	获取价格	描述	数据表
AI60A24-196	ASTEC	获取价格	3-5.5Vdc Input, 1.2Vdc - 3.3Vdc Output 20W DC-DC Converter
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AI60A24-198	ASTEC	获取价格	3-5.5Vdc Input, 1.2Vdc - 3.3Vdc Output 20W DC-DC Converter
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AI60A24-N97	ASTEC	获取价格	3-5.5Vdc Input, 1.2Vdc - 3.3Vdc Output 20W DC-DC Converter
AI60A24-N98	ASTEC	获取价格	3-5.5Vdc Input, 1.2Vdc - 3.3Vdc Output 20W DC-DC Converter
AI60A48-196	ASTEC	获取价格	3-5.5Vdc Input, 1.2Vdc - 3.3Vdc Output 20W DC-DC Converter
AI60A48-197	ASTEC	获取价格	3-5.5Vdc Input, 1.2Vdc - 3.3Vdc Output 20W DC-DC Converter
AI60A48-198	ASTEC	获取价格	3-5.5Vdc Input, 1.2Vdc - 3.3Vdc Output 20W DC-DC Converter
AI60A48-N96	ASTEC	获取价格	3-5.5Vdc Input, 1.2Vdc - 3.3Vdc Output 20W DC-DC Converter

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