Intel® Agilex™ Device Data Sheet
DS-1060 | 2020.05.14
Document
Version
Changes
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Updated the I/O PLL Specifications for Intel Agilex Devices table.
— Added notes for tFCOMP, tOUTPJ_DC, and tOUTCCJ_DC
.
— Removed tINCCJ specifications.
— Added tREFPJ and tREFPN specifications.
— Updated tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, tOUTCCJ_IO, and tCASC_OUTPJ_DC specifications.
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Added a note for fixed-point 27 × 27 multiplication mode in the DSP Block Performance Specifications for Intel Agilex Devices table.
Updated the Memory Block Performance Specifications for Intel Agilex Devices table.
— Updated the specifications for MLAB memory.
— Updated the specifications for M20K block and added low power (LP) specifications.
Updated the specifications in the Remote Temperature Diode Specifications for Intel Agilex Devices (Core Fabric TSD) table.
Added the Remote Temperature Diode Specifications for Intel Agilex Devices (P-Tile TSD) table.
Updated the LVDS SERDES Specifications for Intel Agilex Devices table.
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— Updated the tx Jitter - True Differential I/O Standards specifications for –4 speed grade.
— Removed global, regional, or local in clock routing resource.
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Updated the DPA Lock Time Specifications for Intel Agilex Devices table.
— Updated the description of the table.
— Updated the maximum data transition from 960 to 768.
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Updated the jitter requirements in the Memory Output Clock Jitter Specifications section.
Updated the specifications in the Maximum HPS Clock Frequencies for Intel Agilex Devices table.
Updated the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device
tables.
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Updated the following diagrams:
— USB ULPI Timing Diagram
— RGMII TX Timing Diagram
— RMII TX Timing Diagram
— RMII RX Timing Diagram
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Updated tST0 and tCD2UM specifications in the General Configuration Timing Specifications for Intel Agilex Devices table.
Added notes to Tclk and Tdo specifications in the AS Timing Parameters for Intel Agilex Devices table.
Updated tADSU and tAVSU specifications in the Avalon-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel Agilex Devices table.
Added the following tables:
— Configuration Bit Stream Sizes for Intel Agilex Devices
— Maximum Configuration Time Estimation for Intel Agilex Devices
— Programmable IOE Delay for Intel Agilex Devices
2019.12.18
2019.04.02
Updated the I/O PLL Specifications for Intel Agilex Devices table.
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Removed scanclk from fDYCONFIGCLK parameter.
Corrected the maximum specification for fDYCONFIGCLK from 200 MHz to 100 MHz.
Initial release.
Intel Agilex Device Data Sheet
94
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