AFE1105EA

更新时间： 2024-01-11 13:33:23

品牌	Logo	应用领域
BB		/
页数	文件大小	规格书
10页	208K
描述
Digital SLIC, 1-Func, CMOS, PDSO48,

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技术参数
数据手册

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AFE1105EA 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.81
数据速率：	512 Mbps	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP48,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3/5,5 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	DIGITAL SLIC
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

AFE1105EA 数据手册

rxLOOP INPUT

THEORY OF OPERATION

rxLOOP is the loopback control signal. When enabled, the

rxLINE_Pand rxLINE_Ninputs are disconnected from the

AFE. The rxHYB_Pand rxHYB_Ninputs remain connected.

Loopback is enabled by applying a positive signal (Logic 1)

to rxLOOP.

The transmit channel consists of a switched-capacitor pulse

forming network followed by a differential line driver. The

pulse forming network receives symbol data from the

XMTDA output of the MtH1210B and generates a 2B1Q

output waveform. The output meets the pulse mask and

power spectral density requirements defined in European

Telecommunications Standards Institute document RTR/

TM-03036 for E1 mode and in sections 6.2.1 and 6.2.2.1 of

Bellcore technical advisory TA-NWT-001210 for T1 mode.

The differential line driver uses a composite output stage

combining class B operation (for high efficiency driving

large signals) with class AB operation (to minimize cross-

over distortion).

ECHO CANCELLATION IN THE AFE

The rxHYB input is designed to be subtracted from the

rxLINE input for first order echo cancellation. To accom-

plish this, note that the rxLINE input is connected to the

same polarity signal at the transformer (positive to positive

and negative to negative) while the rxHYB input is con-

nected to opposite polarity through the compromise hybrid

(negative to positive and positive to negative) as shown in

Figure 2.

The receive channel is designed around a fourth-order delta

sigma A/D converter. It includes a difference amplifier

designed to be used with an external compromise hybrid for

first order analog crosstalk reduction. A programmable gain

amplifier with gains of 0dB to +9dB is also included. The

delta sigma modulator operating at a 24X oversampling ratio

produces 14 bits of resolution at output rates up to 584kHz.

The basic functionality of the AFE1105 is illustrated in

Figure 1 shown below.

RECEIVE DATA CODING

The data from the receive channel A/D converter is coded in

two’s complement code.

ANALOG INPUT

OUTPUT CODE (rxD13 - rxD0)

Positive Full Scale

Mid Scale

Negative Full Scale

01111111111111

00000000000000

10000000000000

The receive channel operates by summing the two differen-

tial inputs, one from the line (rxLINE) and the other from the

compromise hybrid (rxHYB). The connection of these two

inputs so that the hybrid signal is subtracted from the line

signal is described in the paragraph titled “Echo Cancella-

tion in the AFE”. The equivalent gain for each input in the

difference amp is 1. The resulting signal then passes to a

programmable gain amplifier which can be set for gains of

0dB through 9dB. The ADC converts the signal to a

14-bit digital word, rxD13-rxD0.

RECEIVE CHANNEL PROGRAMMABLE

GAIN AMPLIFIER

The gain of the amplifier at the input of the Receive Channel

is set by two gain control pins, rxGAIN1 and rxGAIN0. The

resulting gain between 0dB and +9dB is shown below.

rxGAIN1

rxGAIN0

GAIN

0dB

3.25dB

6dB

9dB

txLINE_P

txLINE_N

Pulse Former

txDAT

Differential

Line Driver

rxHYB_P

rxHYB_N

ADC

rxD13 - rxD0

rxLINE_P

rxLINE_N

Programmable

Gain Amp

Difference

Amplifier

FIGURE 1. Functional Block Diagram of AFE1105.

AFE1105

1...3 4 567 8 9 10

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