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AFBR-57D7APZ PDF预览

AFBR-57D7APZ

更新时间: 2022-02-26 13:00:27
品牌 Logo 应用领域
安华高科 - AVAGO /
页数 文件大小 规格书
22页 669K
描述
16GFC SFP Digital Diagnostic SFP, 850 nm, 16G/8G/4G Low Voltage (3.3 V) Fibre Channel Optical Transceiver

AFBR-57D7APZ 数据手册

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Table 3. Pin Description  
Pin  
Name  
Function/Description  
Notes  
1
VeeT  
Transmitter Ground  
2
TX_FAULT  
TX_DISABLE  
MOD-DEF2  
MOD-DEF1  
MOD-DEF0  
Rx Rate Select RS(0)  
RX_LOS  
Tx Rate Select RS(1)  
VeeR  
Transmitter Fault Indication – High indicates a fault condition  
Transmitter Disable – Module electrical input disables on high or open  
Module Definition 2 – Two wire serial ID interface data line (SDA)  
Module Definition 1 – Two wire serial ID interface clock line (SCL)  
Module Definition 0 – Grounded in module (module present indicator)  
Receiver rate select. Logic High = 14.025 Gb/s, Logic Low = 8.5 Gb/s and 4.25 Gb/s  
Loss of Signal – High indicates loss of received optical signal  
Note 1  
Note 2  
Note 3  
Note 3  
Note 3  
Note 8  
Note 4  
3
4
5
6
7
8
9
Transmitter rate select. Logic High = 14.025 Gb/s, Logic Low = 8.5 Gb/s and 4.25 Gb/s Note 8  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Receiver Ground  
Receiver Ground  
VeeR  
RD-  
Inverse Received Data Out  
Received Data Out  
Note 5  
Note 5  
RD+  
VeeR  
Receiver Ground  
VccR  
Receiver Power + 3.3 V  
Transmitter Power + 3.3 V  
Transmitter Ground  
Note 6  
Note 6  
VccT  
VeeT  
TD+  
Transmitter Data In  
Note 7  
Note 7  
TD-  
Inverse Transmitter Data In  
Transmitter Ground  
20  
VeeT  
Notes:  
1. TX_FAULT is an open collector/drain output, which must be pulled up with a 4.7k – 10kΩ resistor on the host board. When high, this output indi-  
cates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to < 0.8V.  
2. TX_DISABLE is an input that is used to shut down the transmitter optical output. It is internally pulled up (within the transceiver) with a 6.8kΩ  
resistor.  
Low (0 – 0.8V):  
Between (0.8V and 2.0V):  
Transmitter on  
Undefined  
High (2.0 – Vcc max) or OPEN: Transmitter Disabled  
3. The signals Mod-Def 0, 1, 2 designate the two wire serial interface pins. They must be pulled up with a 4.7k – 10kΩ resistor on the host board.  
Mod-Def 0 is grounded by the module to indicate the module is present  
Mod-Def 1 is serial clock line (SCL) of two wire serial interface  
Mod-Def 2 is serial data line (SDA) of two wire serial interface  
4. RX_LOS (Rx Loss of Signal) is an open collector/drain output that must be pulled up with a 4.7k – 10kΩ resistor on the host board. When high, this  
output indicates the received optical power is below the worst case receiver sensitivity (as defined by the standard in use). Low indicates normal  
operation. In the low state, the output will be pulled to < 0.8V.  
5. RD-/+ designate the differential receiver outputs. They are AC coupled 100Ω differential lines which should be terminated with 100Ω differential  
at the host SERDES input. AC coupling is done inside the transceiver and is not required on the host board. The voltage swing on these lines will  
be between 370 and 850 mV differential (185 – 425 mV single ended) when properly terminated.  
6. VccR and VccT are the receiver and transmitter power supplies. They are defined at the SFP connector pin. The maximum supply current is 300 mA  
and the associated in-rush current will typically be no more than 30 mA above steady state after 2 microseconds.  
7. TD-/+ designate the differential transmitter inputs. They are AC coupled differential lines with 100 Ω differential termination inside the module.  
The AC coupling is done inside the module and is not required on the host board. The inputs will accept differential swings of 180 – 1200 mV (90  
– 600mV single ended)  
8. Rate_Select is an input that is used to control transmit and receive high speed parametric optimizaton. It is internally pulled down (within the  
transceiver) with a 40kOhm resistor.  
Low (0 - 0.8V) or Open:  
Between (0.8V and 2.0V)  
High (2.0 - Vcc max):  
Rate is set to 8.5Gb/s and below optimization. The CDR is bypassed.  
Undefined  
Rate is set to 14.025Gb/s optimization. The CDR is engaged.  
8

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