ADuM7223
Data Sheet
Parameter
Channel-to-Channel Matching6
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
tPSKCD
VDD2 = 12 V
VDD2 = 4.5 V
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
Refresh Rate
1
1
12
0.05
1.65
1.2
8.5
8.5
24
ns
ns
ns
CL = 2 nF
CL = 2 nF; A-Grade Only
CL = 2 nF, VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
tR/tF
IDDI (D)
IDDO (D)
fr
1
mA/Mbps
mA/Mbps
Mbps
1 Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the Absolute Maximum Ratings.
2 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 16 for waveforms of propagation delay parameters.
5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between ADuM7223 units at the same operating temperature, supply voltages,
and output load within the recommended operating conditions. See Figure 16 for waveforms of propagation delay parameters.
6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All
minimum/maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VDD2 = 12 V.
Switching specifications are tested with CMOS signal levels.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current per Channel, Quiescent
Supply Current at 1 MHz
VDD1 Supply Current
VDDA/VDDB Supply Current
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, VDD1 Supply
Positive Going Threshold
Negative Going Threshold
Hysteresis
IDDI (Q)
IDDO (Q)
0.87
2.3
1.4
3.5
mA
mA
IDD1 (Q)
IDDA (Q), IDDB (Q)
IIA, IIB
VIH
VIL
1.1
5.6
+0.01 +1
1.5
8.0
mA
mA
μA
V
V
V
Up to 1 MHz, no load
Up to 1 MHz, no load
0 V ≤ VIA, VIB ≤ VDD1
−1
0.7 × VDD1
0.3 × VDD1
0.15
VOAH, VOAH
VOAL, VOBL
VDD2 − 0.1 VDD2
0.0
IOx = −20 mA, VIx = VIxH
IOx = 20 mA, VIx = VIxL
V
VDD1UV+
VDD1UV−
VDD1UVH
2.8
2.6
0.2
V
V
V
Undervoltage Lockout, VDD2 Supply
Positive Going Threshold
Negative Going Threshold
Hysteresis
Positive Going Threshold
Negative Going Threshold
Hysteresis
Positive Going Threshold
Negative Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current1
Output Source Resistance
Output Sink Resistance
VDD2UV+
VDD2UV−
VDD2UVH
VDD2UV+
VDD2UV−
VDD2UVH
VDD2UV+
VDD2UV−
VDD2UVH
IOA(SC), IOB(SC)
ROA, ROB
ROA, ROB
4.1
4.4
V
V
V
V
V
V
V
V
V
A
Ω
Ω
A-Grade
A-Grade
A-Grade
B-Grade
B-Grade
B-Grade
C-Grade
C-Grade
3.2
5.7
9.0
3.6
0.5
6.9
6.2
0.7
10.5
9.6
0.9
4.0
0.95
0.6
7.4
11.2
C-Grade
2.0
0.25
0.55
VDD2 = 12 V
VDD2 = 12 V, IOx = −250 mA
VDD2 = 12 V, IOx = 250 mA
1.5
1.35
Rev. A | Page 4 of 16