5秒后页面跳转
捷配首页

Datasheet > ADUM6411
ADUM6411 PDF预览

ADUM6411

更新时间： 2024-02-05 04:53:58
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
29页 874K
描述
集成DC/DC转换器和1个反向通道的鲁棒3.75 kV rms四通道隔离器

阅读下载

获取价格

ADUM6411 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：SSOP,
针数：24Reach Compliance Code：compliant
风险等级：2.14其他特性：ALSO REQUIRE PRIMARY SUPPLY VOLTAGE (VDDP) RANGES FROM 3V TO 5.5V
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：8.2 mm
湿度敏感等级：3功能数量：1
端子数量：24最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
座面最大高度：2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：5.3 mm
Base Number Matches：1

ADUM6411 数据手册

 浏览型号ADUM6411的Datasheet PDF文件第22页浏览型号ADUM6411的Datasheet PDF文件第23页浏览型号ADUM6411的Datasheet PDF文件第24页浏览型号ADUM6411的Datasheet PDF文件第26页浏览型号ADUM6411的Datasheet PDF文件第27页浏览型号ADUM6411的Datasheet PDF文件第28页 
Data Sheet  
ADuM6410/ADuM6411/ADuM6412  
THEORY OF OPERATION  
The dc-to-dc converter section of the ADuM6410/ADuM6411/  
ADuM6412 works on principles that are common to most  
modern power supplies. It has a split controller architecture with  
isolated PWM feedback. VDDP power is supplied to an oscillating  
circuit that switches current into a chip-scale air core transformer.  
Power transferred to the secondary side is rectified and regulated to  
a value between 3.15 V and 5.25 V, depending on the setpoint  
supplied by an external voltage divider (see Equation 1). The  
secondary (VISO) side controller regulates the output by creating a  
PWM control signal that is sent to the primary (VDDP) side by a  
dedicated iCoupler data channel. The PWM modulates the oscilla-  
tor circuit to control the power being sent to the secondary side.  
Feedback allows for significantly higher power and efficiency.  
less than 80% duty factor, leaving no margin to support load or  
temperature variations.  
Typically, the ADuM6410/ADuM6411/ADuM6412 dissipate  
about 17% more power between room temperature and maxi-  
mum temperature; therefore, the 20% PWM margin covers  
temperature variations.  
The ADuM6410/ADuM6411/ADuM6412 implement  
undervoltage lockout (UVLO) with hysteresis on the primary  
and secondary side input/output pins as well as the VDDP power  
input. This feature ensures that the converter does not go into  
oscillation due to noisy input power or slow power-on ramp rates.  
The digital isolator channels use a high frequency carrier to  
transmit data across the isolation barrier using iCoupler chip  
scale transformer coils separated by layers of polyimide isolation.  
Using an on/off keying (OOK) technique and the differential  
architecture shown in Figure 29, the digital isolator channels have  
very low propagation delay and high speed. Internal regulators and  
input/output design techniques allow logic and supply voltages over  
a wide range from 1.7 V to 5.5 V, offering voltage translation of  
1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed for  
high common-mode transient immunity and high immunity to  
electrical noise and magnetic interference. Radiated emissions  
are minimized with a spread spectrum OOK carrier and  
other techniques.  
(R1 R2)  
VISO 1.225 V  
(1)  
R1  
where:  
R1 is a resistor between VSEL and GNDISO  
R2 is a resistor between VSEL and VISO  
.
.
Because the output voltage can be adjusted continuously  
there are an infinite number of operating conditions. This  
data sheet addresses three discrete operating conditions in the  
Specifications section. Many other combinations of input and  
output voltage are possible; Figure 15 shows the supported  
voltage combinations at room temperature. Figure 15 was  
generated by fixing the VISO load and decreasing the input  
voltage until the PWM was at 80% duty cycle. Each of the figures  
represents the minimum input voltage that is required for  
operation under this criterion. For example, if the application  
requires 30 mA of output current at 5 V, the minimum input  
Figure 29 shows the waveforms of the digital isolator channels  
that have the condition of the fail-safe output state equal to low,  
where the carrier waveform is off when the input state is low. If  
the input side is off or not operating, the low fail-safe output state  
sets the output to low.  
voltage at VDDP is 4.25 V. Figure 15 also illustrates why the VDDP  
=
3.3 V input and VISO = 5 V configuration is not recommended.  
Even at 10 mA of output current, the PWM cannot maintain  
REGULATOR  
REGULATOR  
RECEIVER  
TRANSMITTER  
V
V
OUT  
IN  
GND  
GND  
2
1
Figure 29. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State  
Rev. 0 | Page 25 of 29  
 
 
1...2223242526272829

下载PDF

与ADUM6411相关器件

型号 品牌 描述 获取价格 数据表
ADuM6411BRSZ ADI Quad-Channel Isolators with Integrated DC-to-DC Converters

获取价格
ADuM6411BRSZ-RL7 ADI Quad-Channel Isolators with Integrated DC-to-DC Converters

获取价格
ADUM6412 ADI 集成DC/DC转换器和2个反向通道的鲁棒3.75 kV rms四通道隔离器

获取价格
ADuM6412BRSZ ADI Quad-Channel Isolators with Integrated DC-to-DC Converters

获取价格
ADuM6412BRSZ-RL7 ADI Quad-Channel Isolators with Integrated DC-to-DC Converters

获取价格
ADUM6420A ADI Quad-Channel Isolators with Integrated DC-to-DC Converter

获取价格

与ADUM6411相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证