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ADUM5402WCRWZRL PDF预览

ADUM5402WCRWZRL

更新时间: 2024-02-26 05:13:02
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管接口集成电路
页数 文件大小 规格书
24页 529K
描述
SPECIALTY ANALOG CIRCUIT, PDSO16, ROHS COMPLIANT, MS-013AA, SOIC-16

ADUM5402WCRWZRL 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.58接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:10.3 mm湿度敏感等级:3
功能数量:1端子数量:16
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260座面最大高度:2.65 mm
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

ADUM5402WCRWZRL 数据手册

 浏览型号ADUM5402WCRWZRL的Datasheet PDF文件第18页浏览型号ADUM5402WCRWZRL的Datasheet PDF文件第19页浏览型号ADUM5402WCRWZRL的Datasheet PDF文件第20页浏览型号ADUM5402WCRWZRL的Datasheet PDF文件第21页浏览型号ADUM5402WCRWZRL的Datasheet PDF文件第22页浏览型号ADUM5402WCRWZRL的Datasheet PDF文件第24页 
Data Sheet  
ADuM5401W/ADuM5402W/ADuM5403W  
RATED PEAK VOLTAGE  
Symptom  
0V  
The VISO output voltage restarts to an incorrect voltage between  
3.4 V and 4.7 V when power is removed at VDD1 and then reapplied  
between 250 ms and 3 sec later. The error occurs only on restart; it  
does not occur at initial power-up. If the part initializes incorrectly,  
power must be removed for an extended time to allow internal  
nodes to discharge and reset. The amount of time required can  
be several minutes at low temperature; therefore, it is critical to  
avoid allowing the device to initialize improperly.  
Figure 28. Bipolar AC Waveform  
RATED PEAK VOLTAGE  
0V  
Figure 29. DC Waveform  
Cause  
The secondary side band gap reference does not initialize to the  
proper voltage due to a slow slew rate on VISO after the internal  
nodes are precharged during the previous power cycle. The  
secondary side band gap sets the output voltage of the regulator.  
RATED PEAK VOLTAGE  
0V  
NOTES  
Solution  
1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION  
PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE  
WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE.  
THE LIMITINGVALUE CAN BE POSITIVE OR NEGATIVE, BUT THE  
VOLTAGE CANNOT CROSS 0V.  
The slew rate of VISO is determined by the resistive and capacitive  
load present on the output. Designs that attempt to reduce ripple  
by adding capacitance to the VISO output can slow the slew rate  
enough to cause start-up errors. Choose values for bulk capacitance  
based on the effective dc load. Calculate the dc load as the resistive  
equivalent to the current drawn from the VISO line. Determine  
the range of allowable capacitance for the VISO output from  
Figure 31. Choose the bulk capacitance for VISO to achieve the  
application required ripple, unless the value is in the disallowed  
combinations area; then the value must be reduced to avoid  
restart issues.  
Figure 30. Unipolar AC Waveform  
VISO START-UP ISSUES  
An issue with reliable startup was identified in the ADuM5401W/  
ADuM5402W/ADuM5403W components. This issue has been  
addressed in the ADuM5401W-1/ADuM5402W-1/ADuM5403W-  
1 for the current silicon. The ADuM5401W-1/ADuM5402W-1/  
ADuM5403W-1 devices are recommended for all new designs.  
The following description applies only to the original released  
version of these devices. Production of the original release of  
the devices is being continued for existing customers, but it is  
not recommended for new designs.  
100k  
10k  
DISALLOWED  
COMBINATIONS  
The start-up issue in the original release of the ADuM5401W/  
ADuM5402W/ADuM5403W is related to initialization of the  
band gap voltage references on the primary (power input) and  
secondary (power output) sides of the isoPower device and are  
being addressed in future revisions of the silicon. For current  
versions of the silicon, the user must follow these design guide-  
lines to guarantee proper operation of the device.  
1k  
100  
10  
The band gap voltage references are vulnerable to slow power-up  
slew rate. The susceptibility to power-up errors is process sensitive;  
therefore, not all devices display these behaviors. These recommen-  
dations should be implemented for all designs until the corrections  
are made to the silicon. The symptoms and corrective actions  
required for issues with the primary and secondary side startup  
are different.  
1
1
10  
100  
1k  
C
(µF)  
VISO  
Figure 31. Maximum Capacitive Load for Proper Restart  
Rev. D | Page 23 of 24  
 
 
 
 
 

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