Datasheet > ADuM4471

ADuM4471

更新时间： 2024-01-03 07:41:38

品牌	Logo	应用领域
亚德诺 - ADI		稳压器开关
页数	文件大小	规格书
36页	750K
描述
Isolated Switching Regulator with Quad-Channel Isolators

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技术参数
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ADuM4471 技术参数

Source Url Status Check Date：	2013-05-01 14:56:51.04	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
包装说明：	SOP, SOP20,.4	针数：	20
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.72
其他特性：	ALSO WORKS WITH 5 V INPUT;VOUT=(3.3-24 VOLT)	模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制技术：	PULSE WIDTH MODULATION	最大输入电压：	3.6 V
最小输入电压：	3 V	标称输入电压：	3.3 V
JESD-30 代码：	R-PDSO-G20	长度：	15.3 mm
功能数量：	1	端子数量：	20
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP20,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	2.64 mm
子类别：	Other Analog ICs	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	最大切换频率：	515 kHz
技术：	DMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
Base Number Matches：	1

ADuM4471 数据手册

ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474

Data Sheet

The primary side input channels sample the input and send a pulse

to the inactive secondary output. The secondary side converter

begins to accept power from the primary, and the V_ISOvoltage

starts to rise. When the secondary side UVLO is reached, the

secondary side outputs are initialized to their default low state

until data, either a transition or a dc refresh pulse, is received

from the corresponding primary side input. It can take up to

1 µs after the secondary side is initialized for the state of the

output to correlate with the primary side input.

POWER CONSIDERATIONS

Soft Start Mode and Current-Limit Protection

When the ADuM447x first receives power from V_DDA, it is

in soft start mode, and the output voltage, V_ISO, is increased

gradually while it is below the start-up threshold. In soft start

mode, the width of the PWM signal is increased gradually by

the primary converter to limit the peak current during V_ISO

power-up. When the output voltage is larger than the start-

up threshold, the PWM signal can be transferred from the

secondary controller to the primary converter, and the dc-to-

dc converter switches from soft start mode to the normal

PWM control mode. If a short circuit occurs, the push-pull

converter shuts down for about 2 ms and then enters soft start

mode. If, at the end of soft start, a short circuit still exists, the

process is repeated, which is called hiccup mode. If the short

circuit is cleared, the ADuM447x enters normal operation.

Secondary side inputs sample their state and transmit it to the

primary side. Outputs are valid one propagation delay after the

secondary side becomes active.

Because the rate of charge of the secondary side is dependent on

the soft start cycle, loading conditions, input voltage, and output

voltage level selected, take care in the design to allow the converter

to stabilize before valid data is required.

The ADuM447x also have a pulse-by-pulse current limit, which

is active in startup and normal operation and protects the primary

switches, X1 and X2, from exceeding approximately 1.2 A peak.

This current limit also protects the transformer windings.

When power is removed from V_DDA, the primary side converter

and coupler shut down when the UVLO level is reached. The

secondary side stops receiving power and starts to discharge.

The outputs on the secondary side hold the last state that they

received from the primary until either the UVLO level is reached

and the outputs are placed in their default low state, or the outputs

detect a lack of activity from the inputs and the outputs are set

to their default value before the secondary power reaches UVLO.

Data Channel Power Cycle

The ADuM447x data input channels on the primary side and

the data input channels on the secondary side are protected

from premature operation by UVLO circuitry. Below the minimum

operating voltage, the power converter holds its oscillator inactive,

and all input channel drivers and refresh circuits are idle. Outputs

are held in a low state. This is to prevent transmission of undefined

states during power-up and power-down operations.

During the application of power to V_DDA, the primary side

circuitry is held idle until the UVLO preset voltage is reached.

At that time, the data channels are initialized to their default

low output state until they receive data pulses from the

secondary side.

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与ADuM4471相关器件

型号	品牌	描述	获取价格	数据表
ADuM4471ARIZ	ADI	Isolated Switching Regulator with Quad-Channel Isolators	获取价格
ADuM4471ARIZ-RL	ADI	Isolated Switching Regulator with Quad-Channel Isolators	获取价格
ADuM4471CRIZ	ADI	Isolated Switching Regulator with Quad-Channel Isolators	获取价格
ADuM4471CRIZ-RL	ADI	Isolated Switching Regulator with Quad-Channel Isolators	获取价格
ADuM4472	ADI	Isolated Switching Regulator with Quad-Channel Isolators	获取价格
ADuM4472ARIZ	ADI	Isolated Switching Regulator with Quad-Channel Isolators	获取价格

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