Data Sheet
ADuM3223/ADuM4223
APPLICATIONS INFORMATION
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM3223/ADuM4223 component.
PC BOARD LAYOUT
The ADuM3223/ADuM4223 digital isolators require no exter-
nal interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins, as
shown in Figure 19. Use a small ceramic capacitor with a value
between 0.01 μF and 0.1 μF to provide a good high frequency
bypass. On the output power supply pin, VDDA or VDDB, it is
recommended to also add a 10 μF capacitor to provide the
charge required to drive the gate capacitance at the ADuM3223/
ADuM4223 outputs. On the output supply pin, the bypass
capacitor use of vias should be avoided or multiple vias should
be employed to reduce the inductance in the bypassing. The
total lead length between both ends of the smaller capacitor and
the input or output power supply pin should not exceed 5 mm.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM3223/
ADuM4223 components operating under the same conditions.
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal
pad beneath the part, and heat is, therefore, dissipated mainly
through the package pins.
Package thermal dissipation limits the performance of switching
frequency vs. output load, as illustrated in Figure 7 and Figure 8
for the maximum load capacitance that can be driven with a 1 Ω
series gate resistance for different values of output voltage. For
example, this curve shows that a typical ADuM3223 can drive a
large MOSFET with 140 nC gate charge at 8 V output (which is
equivalent to a 17 nF load) up to a frequency of about 300 kHz.
V
V
V
DDA
IA
V
IB
OA
V
GND
B
DD1
GND
NC
NC
1
DISABLE
NC
NC
V
DDB
OUTPUT LOAD CHARACTERISTICS
V
OB
GND
1
GND
The ADuM3223/ADuM4223 output signals depend on the
characteristics of the output load, which is typically an N-channel
MOSFET. The driver output response to an N-channel MOSFET
load can be modeled with a switch output resistance (RSW), an
inductance due to the printed circuit board trace (LTRACE), a series
gate resistor (RGATE), and a gate-to-source capacitance (Cgs), as
shown in Figure 21.
B
Figure 19. Recommended PCB Layout
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output. The ADuM3223/ADuM4223 specify tDLH
(see Figure 20) as the time between the rising input high logic
threshold, VIH, to the output rising 10% threshold. Likewise, the
falling propagation delay, tDHL, is defined as the time between
the input falling logic low threshold, VIL, and the output falling
90% threshold. The rise and fall times are dependent on the
loading conditions and are not included in the propagation
delay, which is the industry standard for gate drivers.
R
R
SW
GATE
V
V
OA
IA
V
ADuM3223/
ADuM4223
O
L
TRACE
C
GS
Figure 21. RLC Model of the Gate of an N-Channel MOSFET
RSW is the switch resistance of the internal ADuM3223/
ADuM4223 driver output, which is about 1.1 Ω. RGATE is the
intrinsic gate resistance of the MOSFET and any external series
resistance. A MOSFET that requires a 4 A gate driver has a
typical intrinsic gate resistance of about 1 Ω and a gate-to-
source capacitance, CGS, of between 2 nF and 10 nF. LTRACE is the
inductance of the printed circuit board trace, typically a value of
5 nH or less for a well-designed layout with a very short and wide
connection from the ADuM3223/ADuM4223 output to the gate
of the MOSFET.
90%
OUTPUT
10%
V
IH
INPUT
V
IL
The following equation defines the Q factor of the RLC circuit,
which indicates how the ADuM3223/ADuM4223 output
responds to a step change. For a well-damped output, Q is
less than 1. Adding a series gate resistance dampens the output
response.
tDHL
tDLH
tR
tF
Figure 20. Propagation Delay Parameters
Rev. 0| Page 15 of 20
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
