ADuM3480/ADuM3481/ADuM3482
Data Sheet
Table 6.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Threshold
Logic High
VIH
VIL
0.7 VDDLx
V
V
Logic Low
0.3 VDDLx
Output Voltages
Logic High
VOH
VOL
II
VDDLx − 0.1
VDDLx − 0.4
3.0
2.8
0.0
0.2
V
V
V
V
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDLx, 0 V ≤ VCTRLx ≤ VDDLx
Logic Low
0.1
0.4
+10
Input Current per Channel
Supply Current per Channel
Quiescent Supply Current
Regulator Input Side
I/O Input
−10
+0.01
µA
IDDI (Q)
0.36
0.019
1.21
0.5
0.050
1.7
mA
mA
mA
mA
IDDIL (Q)
IDDO (Q)
IDDOL (Q)
Regulator Output Side
I/O Output
0.021
0.050
Dynamic Supply Current
Regulator Input Side
I/O Input
Regulator Output Side
I/O Output
IDDI (D)
0.070
0.53
0.010
0.013
mA/Mbps
µA/Mbps
mA/Mbps
mA/Mbps
IDDIL (D)
IDDO (D)
IDDOL (D)
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity1
tR/tF
|CM|
3
35
ns
kV/µs
10% to 90%
VIx = VDDLx, VCM = 1000 V,
transient magnitude = 800 V
25
Refresh Period
tr
1.66
µs
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew
rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 6 of 20