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ADUM3474ARSZ-RL7 PDF预览

ADUM3474ARSZ-RL7

更新时间： 2024-01-27 22:41:44
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管接口集成电路
页数 文件大小 规格书
36页 822K
描述
Isolated Switching Regulators (0/4 Channel Directionality)

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ADUM3474ARSZ-RL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP,针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.57
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：7.2 mm
湿度敏感等级：1功能数量：1
端子数量：20最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：2 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：5.3 mmBase Number Matches：1

ADUM3474ARSZ-RL7 数据手册

 浏览型号ADUM3474ARSZ-RL7的Datasheet PDF文件第1页浏览型号ADUM3474ARSZ-RL7的Datasheet PDF文件第2页浏览型号ADUM3474ARSZ-RL7的Datasheet PDF文件第3页浏览型号ADUM3474ARSZ-RL7的Datasheet PDF文件第5页浏览型号ADUM3474ARSZ-RL7的Datasheet PDF文件第6页浏览型号ADUM3474ARSZ-RL7的Datasheet PDF文件第7页 
ADuM3470/ADuM3471/ADuM3472/ADuM3473/ADuM3474  
Data Sheet  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
µA  
V
V
V
Test Conditions/Comments  
I/O Input Currents  
IIA, IIB, IIC, IID −20  
VIH  
VIL  
VOAH, VOBH  
+0.01  
+20  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
2.0  
0.8  
,
V
DD1 − 0.3, 5.0  
IOx = −20 µA, VIx = VIxH  
Ox = −4 mA, VIx = VIxH  
VOCH, VODH  
VISO − 0.3  
VDD1 − 0.5, 4.8  
V
V
V
I
V
ISO − 0.5  
Logic Low Output Voltages  
VOAL, VOBL  
VOCL, VODL  
,
0.0  
0.0  
0.1  
0.4  
IOx = 20 µA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
AC SPECIFICATIONS  
A Grade  
CL = 15 pF, CMOS signal levels  
Minimum Pulse Width  
Maximum Data Rate  
Propagation Delay  
Pulse Width Distortion, |tPLH − tPHL  
Propagation Delay Skew  
Channel-to-Channel Matching  
C Grade  
PW  
1000  
ns  
Mbps  
ns  
ns  
ns  
1
tPHL, tPLH  
PWD  
tPSK  
55  
100  
40  
50  
|
tPSKCD/tPSKOD  
50  
ns  
CL = 15 pF, CMOS signal levels  
Minimum Pulse Width  
Maximum Data Rate  
Propagation Delay  
PW  
40  
ns  
Mbps  
ns  
ns  
ps/°C  
ns  
25  
30  
tPHL, tPLH  
PWD  
45  
5
60  
8
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew  
Channel-to-Channel Matching  
Codirectional Channels  
Opposing Directional Channels  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity  
|
tPSK  
15  
tPSKCD  
tPSKOD  
tR/tF  
8
15  
ns  
ns  
ns  
2.5  
CL = 15 pF, CMOS signal levels  
VCM = 1000 V, transient  
magnitude = 800 V  
At Logic High Output  
At Logic Low Output  
Refresh Rate  
|CMH|  
|CML|  
fr  
25  
25  
35  
35  
1.0  
kV/µs  
kV/µs  
Mbps  
VIx = VDD1 or VISO  
VIx = 0 V  
1 The contributions of supply current values for all four channels are combined at identical data rates.  
2 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current  
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the  
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.  
3 The power demands of the quiescent operation of the data channels is not separated from the power supply section. Efficiency includes the quiescent power  
consumed by the I/O channels as part of the internal power consumption.  
4 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load  
representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of the available current at less than the maximum data rate.  
Rev. B | Page 4 of 36  
 
 
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