Datasheet > ADuM250N0BRIZ-RL

ADuM250N0BRIZ-RL

更新时间： 2024-02-04 22:57:53

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亚德诺 - ADI		/
页数	文件大小	规格书
22页	554K
描述
High common-mode transient immunity: 100 kV/Î¼s

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ADuM250N0BRIZ-RL 数据手册

Data Sheet

ADuM250N/ADuM251N/ADuM252N

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 5 V. Minimum/maximum specifications apply over the entire recommended

operation range of 4.5 V ≤ V_DD1≤ 5.5 V, 4.5 V ≤ V_DD2≤ 5.5 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications

are tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 1.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

6.6

150

4.8

Mbps

ps/°C

Within pulse width distortion (PWD) limit

Within PWD limit

50% input to 50% output

Data Rate¹

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

t_PHL, t_PLH

PWD

7.2

0.5

1.5

4.5

|t_PLH− t_PHL|

t_PSK

6.1

Between any two units at the

same temperature, voltage, and load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

0.5

490

4.0

4.5

ps p-p

ps rms

See the Jitter Measurement section

DC SPECIFICATIONS

Input Threshold Voltage

Logic High

V_IH

V_IL

0.7 ×

V_DDx

Logic Low

0.3 ×

V_DDx

Output Voltage

Logic High

V_OH

V_DDx− 0.1 V_DDx

V_DDx− 0.4 V_DDx

0.2

I_Ox²= −20 µA, V_Ix= V_IxH

−

I_Ox²= −4 mA, V_Ix= V_IxH

Logic Low

V_OL

I_I

0.0

0.2

0.1

0.4

+10

µA

I_Ox²= 20 µA, V_Ix= V_IxL

I_Ox²= 4 mA, V_Ix= V_IxL

Input Current per Channel

Quiescent Supply Current

ADuM250N

−10

+0.01

0 V ≤ V_Ix≤ V_DDx

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

2.54

3.34

16.8

3.57

3.70

4.56

27.5

4.90

V_I⁵= 0 (N0), 1 (N1)⁶

V_I⁵= 1 (N0), 0 (N1)⁶

ADuM251N

ADuM252N

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

2.79

3.20

14.2

7.08

4.09

4.22

V_I⁵= 0 (N0), 1 (N1)⁶

V_I⁵= 1 (N0), 0 (N1)⁶

11.1

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

2.91

2.95

11.1

10.5

4.11

4.15

19.5

16.7

V_I⁵= 0 (N0), 1 (N1)⁶

V_I⁵= 1 (N0), 0 (N1)⁶

Dynamic Supply Current

Dynamic Input

Dynamic Output

Inputs switching, 50% duty cycle

I_{DDI (D)}

I_{DDO (D)}

0.01

0.02

mA/Mbps

Rev. 0 | Page 3 of 22

1 234 5 6 7...22

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