Data Sheet
ADuM230D/ADuM230E/ADuM231D/ADuM231E
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity7
tR/tF
|CMH|
2.5
100
ns
kV/μs
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
75
75
|CML|
100
kV/μs
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, or C.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 refers to the ADuM230E0/ADuM231E0 models, D0 refers to the ADuM230D0/ADuM231D0 models, E1 refers to the ADuM230E1/ADuM231E1 models, and D1 refers
to the ADuM230D1/ADuM231D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VOx) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VOx > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 6. Total Supply Current vs. Data Throughput
1 Mbps
Typ
25 Mbps
Typ
100 Mbps
Typ
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
SUPPLY CURRENT
ADuM230D/ADuM230E
Supply Current Side 1
Supply Current Side 2
ADuM231D/ADuM231E
Supply Current Side 1
Supply Current Side 2
IDD1
IDD2
5.3
1.8
8.7
3.6
5.9
2.6
9.3
4.4
8.2
5.2
12.3
7.4
mA
mA
IDD1
IDD2
4.4
3.4
7.1
5.6
5.0
4.1
7.8
6.3
7.5
6.6
10.1
8.7
mA
mA
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
6.6
150
5.8
ns
Mbps
ns
ns
ps/°C
ns
Within PWD limit
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
tPHL, tPLH
PWD
8.7
0.7
1.5
15
3
tPSK
7.0
Between any two devices at the same
temperature, voltage, and load
Channel Matching
Codirectional
Opposing Direction
Jitter
tPSKCD
tPSKOD
0.7
0.7
600
90
3.0
3.0
ns
ns
ps p-p
ps rms
See the Jitter Measurement section
See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
VIH
VIL
0.7 × VDDx
V
V
Logic Low
0.3 × VDDx
Rev. A | Page 7 of 21
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