ADuM220N/ADuM221N/ADuM225N/ADuM226N
Data Sheet
APPLICATIONS INFORMATION
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
PCB LAYOUT
The ADuM220N/ADuM221N/ADuM225N/ADuM226N
digital isolators require no external interface circuitry for the
logic interfaces. Power supply bypassing is strongly recom-
mended at the input and output supply pins (see Figure 19 and
Figure 20). For the ADuM225N/ADuM226N, bypass capacitors
are most conveniently connected between Pin 1 and Pin 4 for
Channel matching is the maximum amount the propagation
delay differs between channels within a single ADuM220N/
ADuM221N/ADuM225N/ADuM226N component.
Propagation delay skew is the maximum amount the propaga-
tion delay differs between multiple ADuM220N/ADuM221N/
ADuM225N/ADuM226N components operating under the
same conditions.
VDD1 and between Pin 5 and Pin 8 for VDD2. For the ADuM220N/
ADuM221N, bypass capacitors are most conveniently con-
nected between Pin 1 and Pin 3 for VDD1 and between Pin 14
and Pin 16 for VDD2. The recommended bypass capacitor value is
between 0.01 µF and 0.1 µF. The total lead length between both
ends of the capacitor and the input power supply pin must not
exceed 10 mm. For the ADuM220N/ADuM221N, bypassing
between Pin 3 and Pin 7 and between Pin 9 and Pin 14 must
also be considered, unless the ground pair on each package side
are connected close to the package.
JITTER MEASUREMENT
Figure 22 shows the eye diagram for the ADuM220N/
ADuM221N/ADuM225N/ADuM226N. The measurement
was taken using an Agilent 81110A pulse pattern generator at
150 Mbps with pseudorandom bit sequences (PRBS) 2(n − 1),
n = 14, for 5 V supplies. Jitter was measured with the Tektronix
Model 5104B oscilloscope, 1 GHz, 10 GSPS with the DPOJET
jitter and eye diagram analysis tools. The result shows a typical
measurement on the ADuM220N/ADuM221N/ADuM225N/
ADuM226N with 380 ps p-p jitter.
GND
GND
1
2
NIC
NIC
V
V
DD2
DD1
V
, V
V
, V
OA IA
OB
IA OA
V
V
IB
NIC
NIC
NIC
GND
5
4
3
2
1
0
GND
1
NIC
2
Figure 19. Recommended PCB Layout for ADuM220N/ADuM221N
V
V
V
V
, V
DD2
DD1
V
, V
IA OA
OA IA
OB
V
IB
GND
1
GND
2
Figure 20. Recommended PCB Layout for ADuM225N/ADuM226N
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
–10
–5
0
5
10
TIME (ns)
Figure 22. ADuM220N/ADuM221N/ADuM225N/ADuM226N Eye Diagram
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insula-
tion degradation is dependent on the characteristics of the voltage
waveform applied across the insulation as well as on the materials
and material interfaces.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation
wear out. Surface breakdown is the phenomenon of surface
tracking, and the primary determinant of surface creepage
requirements in system level standards. Insulation wear out is the
phenomenon where charge injection or displacement currents
inside the insulation material cause long-term insulation
degradation.
INPUT (V
)
50%
Ix
tPLH
tPHL
OUTPUT (V
)
50%
Ox
Figure 21. Propagation Delay Parameters
Rev. 0 | Page 20 of 23
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