ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
65
5
Pulse-Width Distortion, |tPLH – tPHL
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM140xBRW
|
40
50
50
ns
ns
ns
tPSKCD/OD
Minimum Pulse Width3
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
10
20
Propagation Delay5
tPHL, tPLH
PWD
32
5
50
3
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
15
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM140xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
27
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
18
Propagation Delay5
tPHL, tPLH
PWD
32
2
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
10
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output8
t
PHZ, tPLH
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tPZH, tPZL
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
Common-Mode Transient Immunity
at Logic Low Output8
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current, per Channel9
Output Dynamic Supply Current, per Channel9
IDDI (D)
IDDO (D)
0.19
0.05
mA/Mbps
mA/Mbps
See Notes on next page.
Rev. B | Page 4 of 24