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ADUM1400WSRWZ35

更新时间： 2024-01-30 12:01:07
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管接口集成电路
页数 文件大小 规格书
31页 623K
描述
Interface Circuit, CMOS, PDSO16

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ADUM1400WSRWZ35 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：SOP,Reach Compliance Code：compliant
风险等级：5.56接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G16长度：10.3 mm
功能数量：4端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：2.65 mm
最大供电电压：5.5 V最小供电电压：3 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

ADUM1400WSRWZ35 数据手册

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Data Sheet  
ADuM1400/ADuM1401/ADuM1402  
APPLICATIONS INFORMATION  
PC BOARD LAYOUT  
DC CORRECTNESS AND MAGNETIC FIELD  
IMMUNITY  
The ADuM1400/ADuM1401/ADuM1402 digital isolators  
require no external interface circuitry for the logic interfaces.  
Power supply bypassing is strongly recommended at the input  
and output supply pins (see Figure 17). Bypass capacitors are  
most conveniently connected between Pin 1 and Pin 2 for VDD1  
and between Pin 15 and Pin 16 for VDD2. The capacitor value  
should be between 0.01 µF and 0.1 µF. The total lead length  
between both ends of the capacitor and the input power supply  
pin should not exceed 20 mm. Bypassing between Pin 1 and Pin  
8 and between Pin 9 and Pin 16 should also be considered,  
unless the ground pair on each package side is connected close  
to the package.  
Positive and negative logic transitions at the isolator input  
cause narrow (~1 ns) pulses to be sent to the decoder via the  
transformer. The decoder is bistable and is, therefore, either set  
or reset by the pulses, indicating input logic transitions. In the  
absence of logic transitions at the input for more than ~1 µs, a  
periodic set of refresh pulses indicative of the correct input state  
are sent to ensure dc correctness at the output. If the decoder  
receives no internal pulses of more than about 5 µs, the input  
side is assumed to be unpowered or nonfunctional, in which  
case the isolator output is forced to a default state (see Table 15)  
by the watchdog timer circuit.  
V
GND  
V
V
DD2  
DD1  
The limitation on the magnetic field immunity of the ADuM1400/  
ADuM1401/ADuM1402 is set by the condition in which induced  
voltage in the receiving coil of the transformer is sufficiently large  
enough to either falsely set or reset the decoder. The following  
analysis defines the conditions under which this may occur. The  
3 V operating condition of the ADuM1400/ADuM1401/  
ADuM1402 is examined because it represents the most susceptible  
mode of operation.  
GND  
1
2
V
IA  
IB  
OA  
V
V
OB  
V
V
/V  
V
V
V
V
IC OC  
OC/ IC  
V
V
ID/ OD  
OD/ ID  
NC/V  
E1  
E2  
GND  
GND  
2
1
Figure 17. Recommended Printed Circuit Board Layout  
In applications involving high common-mode transients, care  
should be taken to ensure that board coupling across the isolation  
barrier is minimized. Furthermore, the board layout should be  
designed such that any coupling that does occur equally affects  
all pins on a given component side. Failure to ensure this could  
cause voltage differentials between pins exceeding the Absolute  
Maximum Ratings of the device, thereby leading to latch-up or  
permanent damage.  
The pulses at the transformer output have an amplitude greater  
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus  
establishing a 0.5 V margin in which induced voltages can be  
tolerated. The voltage induced across the receiving coil is given by  
2
V = (−dβ/dt)∑∏rn ; n = 1, 2, … , N  
where:  
β is magnetic flux density (gauss).  
N is the number of turns in the receiving coil.  
rn is the radius of the nth turn in the receiving coil (cm).  
See the AN-1109 Application Note for board layout guidelines.  
PROPAGATION DELAY-RELATED PARAMETERS  
Propagation delay is a parameter that describes the time it takes  
a logic signal to propagate through a component. The propagation  
delay to a Logic 0 output may differ from the propagation delay  
to a Logic 1 output.  
Given the geometry of the receiving coil in the ADuM1400/  
ADuM1401/ADuM1402 and an imposed requirement that the  
induced voltage be 50% at most of the 0.5 V margin at the  
decoder, a maximum allowable magnetic field is calculated as  
shown in Figure 19.  
INPUT (V  
)
50%  
Ix  
100  
tPLH  
tPHL  
OUTPUT (V  
)
50%  
Ox  
10  
1
Figure 18. Propagation Delay Parameters  
Pulse width distortion is the maximum difference between  
these two propagation delay values and is an indication of how  
accurately the timing of the input signal is preserved.  
0.1  
Channel-to-channel matching refers to the maximum amount  
the propagation delay differs between channels within a single  
ADuM1400/ADuM1401/ADuM1402 component.  
0.01  
0.001  
Propagation delay skew refers to the maximum amount the  
propagation delay differs between multiple ADuM1400/  
ADuM1401/ADuM1402 components operating under the same  
conditions.  
1k  
10k  
100k  
1M  
10M  
100M  
MAGNETIC FIELD FREQUENCY (Hz)  
Figure 19. Maximum Allowable External Magnetic Flux Density  
Rev. L | Page 27 of 31  
 
 
 
 
 
 
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