ADuM1400/ADuM1401/ADuM1402
APPLICATIONS INFORMATION
PC BOARD LAYOUT
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
The ADuM140x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 17). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The capacitor value should be between 0.01 μF and
0.1 μF. The total lead length between both ends of the capacitor
and the input power supply pin should not exceed 20 mm.
Bypassing between Pin 1 and Pin 8 and between Pin 9 and
Pin 16 should also be considered, unless the ground pair on
each package side is connected close to the package.
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 15)
by the watchdog timer circuit.
V
V
DD1
DD2
GND
GND
1
IA
IB
2
The limitation on the magnetic field immunity of the ADuM140x
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large enough to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this may occur. The 3 V operating
condition of the ADuM140x is examined because it represents
the most susceptible mode of operation.
V
V
V
V
V
V
V
OA
OB
V
/V
V
IC OC
OC/ IC
V
V
V
ID/ OD
NC/V
OD/ ID
E1
GND
E2
GND
1
2
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the Absolute
Maximum Ratings of the device, thereby leading to latch-up or
permanent damage.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
2
V = (−dβ/dt)∑∏rn ; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output may differ from the propagation delay
to a Logic 1 output.
Given the geometry of the receiving coil in the ADuM140x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 19.
100
INPUT (V
)
50%
Ix
tPLH
tPHL
OUTPUT (V
)
50%
Ox
10
1
Figure 18. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
0.1
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM140x component.
0.01
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM140x
components operating under the same conditions.
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 19. Maximum Allowable External Magnetic Flux Density
Rev. G | Page 27 of 32
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