ADUC7036

更新时间： 2024-02-23 02:11:16

品牌	Logo	应用领域
亚德诺 - ADI		电池传感器
页数	文件大小	规格书
140页	928K
描述
Integrated Precision Battery Sensor for Automotive

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数据手册

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ADUC7036 数据手册

Preliminary Technical Data

ADuC7036

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

From MCU Power-Down

Oscillator Running

Wake Up from Interrupt

Wake Up from LIN

Crystal Powered Down

Wake Up from Interrupt

Internal PLL Lock Time

LIN INPUT/OUTPUT GENERAL

Baud Rate

500

1000

20,000

Bits/sec

VDD

Supply voltage range at which the LIN interface

is functional

Input Capacitance

5.5

µA

µs

Input Leakage Current

LIN Comparator Response Time¹

I_{LIN DOM MAX}

Input (low) = IO_VSS

Using 22 Ω resistor

Current limit for driver when LIN bus is in

dominant state, V_BAT= V_{BAT (MAX)}

−800

−400

200

I_{LIN_PAS_REC}

I_LIN

I_{LIN_PAS_DOM}

I_{LIN_NO_GND}

Driver off; 7.0 V < V_LIN< 18 V; V_DD= V_LIN− 0.7 V

VBAT disconnected, V_DD= 0 V, 0 < V_LIN< 18 V

Input leakage V_LIN= 0 V

Control unit disconnected from ground,

GND = V_DD; 0 V < V_LIN< 18 V; V_BAT= 12 V

LIN receiver dominant state, V_DD> 7.0 V

LIN receiver recessive state, V_DD> 7.0 V

LIN receiver center voltage, V_DD> 7.0 V

LIN receiver hysteresis voltage

−20

+20

µA

−1

V_{LIN_DOM}

V_{LIN_REC}

0.4 V_DD

0.6 V_DD

0.475 V_DD0.5 V_DD

V_{LIN_CNT}

0.525 V_DD

0.175 V_DD

V_HYS

V_{LIN_DOM_DRV_LOSUP}

LIN dominant output voltage, V_DD= 7 V

R_L500 Ω

R_L1000 Ω

V_{LIN_DOM_DRV_HISUP}

1.2

0.6

LIN dominant output voltage, V_DD= 18 V

LIN recessive output voltage

R_L500 Ω

R_L1000 Ω

V_{LIN_RECESSIVE}

V_BATShift²⁹

GND Shift²⁹

R_SLAVE

kΩ

0.8

0.8 V_DD

0.4

−2

0.1 V_DD

Slave termination resistance

Voltage drop at the Serial Diode D_{Ser_Int}

V_{DD (MIN)}= 7 V

0.7

V_{SERIAL DIODE}

Symmetry of Transmit

µs

Propagation Delay¹

Receive Propagation Delay¹

V_{DD (MIN)}= 7 V

µs

Symmetry of Receive Propagation

Delay¹

−2

LIN VERSION 2.0 SPECIFICATION

Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ;

6.8 nF||660 Ω; 10 nF||500 Ω

Duty Cycle 1,

0.396

TH_REC(MAX)= 0.744 × V_BAT

TH_DOM(MAX)= 0.581 × V_BAT

V_SUP= 7.0 V . . . 18 V; t_BIT= 50 µs,

D1 = t_{BUS_REC(MIN)}/(2 × t_BIT)

Duty Cycle 2,

0.581

1236

TH_REC(MIN)= 0.284 × V_BAT

TH_DOM(MIN)= 0.422 × V_BAT

_SUP= 7.0 V . . . 18 V; t_BIT= 50 µs,

D2 = t_{BUS_REC(MAX)}/(2 × t_BIT)

BSD INPUT/OUTPUT³⁰

Baud Rate

1164

1200

Bits/sec

Rev. Pr.A | Page 7 of 140

1...4 5 678 9 10...140

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