ADuC7036
Preliminary Technical Data
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.5 V to 18 V, VREF = 1.2 V internal reference, fCORE = 10.24 MHz driven from external 32.768 kHz watch crystal or on-chip
precision oscillator, all specifications TA = −40°C to +115°C, unless otherwise noted.
Table 1. ADuC7036 Electrical Specifications
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADC SPECIFICATIONS
Conversion Rate1
Chop off, ADC normal operating mode
Chop on, ADC normal operating mode
Chop on, ADC low power mode
4
4
1
8000
2600
650
Hz
Hz
Hz
Current Channel
No Missing Codes1
Integral Nonlinearity1, 2
Offset Error2, 3, 4, 5
Offset Error1, 3, 6
Valid for all ADC update rates and ADC modes
16
Bits
ppm of FSR
LSB
μV
nV
10
3
0.5
−50
60
+10
+2
Chop off, 1 LSB = (36.6/gain) μV
Chop on
Chop on, low power or low power plus mode,
MCU powered down
Chop on, normal mode, CD = 1
Chop off, valid for ADC gains of 4 to 64, normal
mode
Chop off, valid for ADC gains of 128 to 512,
normal mode
Chop on
Normal mode
Low power mode, using ADCREF MMR
Low power-plus mode, using precision VREF
−10
−2
100
Offset Error1, 3
−300
Offset Error1, 3
Offset Error Drift6
0.5
−1.25
0.03
−3
μV
LSB/°C
Offset Error Drift6
30
nV/°C
Offset Error Drift6
10
nV/°C
%
%
Total Gain Error1, 3, 7, 8, 9, 10
Total Gain Error1, 3, 7, 9
Total Gain Error1, 3, 7, 9, 11
Gain Drift
−0.5
−4
−1
0.1
0.2
0.2
3
0.1
60
+0.5
+4
+1
%
ppm/°C
%
PGA Gain Mismatch Error
Output Noise1, 12, 13
4 Hz update rate, gain = 512, chop enabled
4 Hz update rate, gain = 512, chop disabled
10 Hz update rate, gain = 512, chop enabled
10 Hz update rate, gain = 512, chop disabled
1 kHz update rate, gain ≥ 64, chop enabled
1 kHz update rate, gain ≥ 64, (ADCFLT = 0x0101)
1 kHz update rate, gain = 512, chop disabled
1 kHz update rate, gain = 32, chop disabled
1 kHz update rate, gain = 8, chop enabled
1 kHz update rate, gain = 8, chop disabled
1 kHz update rate, gain = 8, (ADCFLT = 0x0101)
1 kHz update rate, gain = 4, chop disabled
8 kHz update rate, gain = 32
90
nV rms
nV rms
nV rms
nV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
75
115
150
180
1.2
1.5
0.9
1.2
4.1
2.4
3.9
2.8
3.5
21
100
120
0.8
1
0.6
0.8
2.1
1.6
2.6
2.0
2.5
14
8 kHz update rate, gain = 4
ADC low power mode, fADC = 10 Hz, gain = 128
ADC low power mode, fADC = 1 Hz, gain = 128
ADC low power-plus mode, fADC = 1 Hz, gain = 512
ADC low power-plus mode, fADC = 250 Hz,
gain = 512, chop enabled
1.25
0.35
0.1
0.6
1.9
0.5
0.15
0.9
Voltage Channel14
No Missing Codes1
Integral Nonlinearity1
Offset Error3, 5
Valid at all ADC update rates
16
Bits
ppm of FSR
LSB
LSB
LSB/°C
10
1
0.3
0.03
60
+10
1
Chop off, 1 LSB = 439.5 µV
Chop on
Chop off
−10
Offset Error1, 3
Offset Error Drift
Rev. PrA | Page 4 of 140
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