ADuC7036
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Processor Reference Peripherals................................................... 73
Interrupt System......................................................................... 73
Timers .............................................................................................. 75
Timer0—Lifetime Timer........................................................... 76
Timer1.......................................................................................... 79
Timer2 or Wake-Up Timer....................................................... 81
Timer3 or Watchdog Timer...................................................... 83
Timer4 or STI Timer.................................................................. 85
General-Purpose I/O ..................................................................... 87
High Voltage Peripheral Control Interface ................................. 98
Wake UP (WU) ........................................................................ 105
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 4
Electrical Specifications............................................................... 4
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Typical Performance Characteristics ........................................... 19
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
Overview of the ARM7TDMI Core......................................... 21
Memory Organization ............................................................... 23
Reset ............................................................................................. 25
Flash/EE Memory........................................................................... 26
Flash/EE Control Interface........................................................ 26
Flash/EE Memory Security ....................................................... 30
Flash/EE Memory Reliability.................................................... 32
CODE Execution time from SRAM and Flash/EE ................ 33
ADuC7036 Kernel...................................................................... 34
Memory Mapped Registers ....................................................... 36
Complete MMR Listing............................................................. 37
16-Bit, Σ-∆ Analog-to-Digital Converters .................................. 42
ADC Ground Switch.................................................................. 45
ADC Noise Performance Tables............................................... 46
ADC MMR Interface ................................................................. 47
ADC Power Modes of Operation............................................. 59
ADC Diagnostics........................................................................ 64
Power Supply Support Circuits..................................................... 65
ADuC7036 System Clocks ............................................................ 66
Low Power Clock Calibration................................................... 70
Handling Interrupts from the High Voltage Peripheral
Control Interface ...................................................................... 106
Low Voltage Flag (LVF)........................................................... 106
High Voltage Diagnostics........................................................ 106
UART Serial Interface.................................................................. 107
Baud Rate Generation.............................................................. 107
UART Register Definition....................................................... 107
Serial Peripheral Interface........................................................... 113
MISO (Master In, Slave Out Data I/O Pin) .......................... 113
MOSI (Master Out, Slave In Pin)........................................... 113
SCLK (Serial Clock I/O Pin)................................................... 113
SS
Chip Select ( ) Input Pin...................................................... 113
SPI Register Definitions .......................................................... 113
Serial Test Interface ...................................................................... 117
LIN (Local Interconnect Network) Interface............................ 121
LIN MMR Description............................................................ 121
LIN Hardware Interface .......................................................... 126
Bit Serial Device (BSD) Interface ............................................... 130
BSD Communication Hardware Interface............................ 130
BSD Related MMRs ................................................................. 131
BSD Communications Frame................................................. 132
Rev. PrA| Page 2 of 140
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