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ADT7519ARQZ1-REEL7 PDF预览

ADT7519ARQZ1-REEL7

更新时间: 2022-11-26 05:13:39
品牌 Logo 应用领域
亚德诺 - ADI 传感器温度传感器
页数 文件大小 规格书
44页 1873K
描述
SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC

ADT7519ARQZ1-REEL7 数据手册

 浏览型号ADT7519ARQZ1-REEL7的Datasheet PDF文件第35页浏览型号ADT7519ARQZ1-REEL7的Datasheet PDF文件第36页浏览型号ADT7519ARQZ1-REEL7的Datasheet PDF文件第37页浏览型号ADT7519ARQZ1-REEL7的Datasheet PDF文件第39页浏览型号ADT7519ARQZ1-REEL7的Datasheet PDF文件第40页浏览型号ADT7519ARQZ1-REEL7的Datasheet PDF文件第41页 
ADT7516/ADT7517/ADT7519  
V
V
DD  
DD  
ADT7516/  
ADT7517/  
ADT7519  
ADT7516/  
ADT7517/  
ADT7519  
LOCK AND  
SELECT SPI  
10kΩ  
10kΩ  
CS  
CS  
SDA  
SCL  
V
DD  
SPI FRAMING  
EDGE  
2
820820820Ω  
I C ADDRESS = 1001 000  
ADD  
DIN  
SCLK  
DOUT  
Figure 57. Typical I2C Interface Connection  
Figure 58. Typical SPI Interface Connection  
A
B
C
CS  
(START HIGH)  
SPI LOCKED ON  
THIRD RISING EDGE  
SPI FRAMING  
EDGE  
A
B
C
CS  
(START LOW)  
SPI LOCKED ON  
THIRD RISING EDGE  
SPI FRAMING  
EDGE  
Figure 59. Serial Interface—Selecting and Locking SPI Protocol  
I2C Serial Interface  
a 7-bit address (MSB first) plus a R/ bit, which  
W
determines the direction of the data transfer, i.e., whether  
data will be written to or read from the slave device.  
Like all I2C compatible devices, the ADT7516/ADT7517/  
ADT7519 have a 7-bit serial address. The four MSBs of this  
address for the ADT7516/ADT7517/ADT7519 are set to 1001.  
The three LSBs are set by Pin 11, ADD. The ADD pin can be  
configured three ways to give three different address options:  
low, floating, and high. Setting the ADD pin low gives a serial  
bus address of 1001 000, leaving it floating gives the address  
1001 010, and setting it high gives the address 1001 011. The  
recommended pull-up resistor value is 10 kΩ.  
The peripheral whose address corresponds to the  
transmitted address responds by pulling the data line low  
during the low period before the ninth clock pulse, known  
as the Acknowledge Bit. All other devices on the bus now  
remain idle while the selected device waits for data to be  
read from or written to it. If the R/ bit is 0 the master will  
W
write to the slave device. If the R/ bit is 1, the master will  
W
There is an enable/disable bit for the SMBus timeout. When this  
is enabled, the SMBus will time out after 25 ms of no activity. To  
enable it, set Bit 6 of the Control Configuration 2 register. The  
power-on default is with the SMBus timeout disabled.  
read from the slave device.  
2. Data is sent over the serial bus in sequences of nine clock  
pulses: eight bits of data followed by an acknowledge bit  
from the receiver of data. Transitions on the data line must  
occur during the low period of the clock signal and remain  
stable during the high period, because a low to high tran-  
sition when the clock is high may be interpreted as a stop  
signal.  
The ADT7516/ADT7517/ADT7519 support SMBus packet  
error checking (PEC), but its use is optional. It is triggered by  
supplying the extra clocks for the PEC byte. The PEC is  
calculated using CRC-8. The frame clock sequence (FCS)  
conforms to CRC-8 by the polynominal  
3. When all data bytes have been read or written, stop  
conditions are established. In write mode, the master will  
pull the data line high during the 10th clock pulse to assert  
a stop condition. In read mode, the master device will pull  
the data line high during the low period before the ninth  
clock pulse. This is known as No Acknowledge. The master  
will then take the data line low during the low period  
before the 10th clock pulse, and then high during the 10th  
clock pulse to assert a stop condition.  
C x  
( )  
= x8 + x2 + x1 +1  
Consult the SMBus specification (www.smbus.org) for more  
information.  
The serial bus protocol operates as follows:  
1. The master initiates a data transfer by establishing a start  
condition, defined as a high to low transition on the serial  
data line SDA while the serial clock line SCL remains high.  
This indicates that an address/data stream will follow. All  
slave peripherals connected to the serial bus respond to the  
start condition and shift in the next eight bits, consisting of  
Rev. A | Page 38 of 44  

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