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ADT7519ARQ-REEL7

更新时间： 2024-01-11 10:47:16
品牌 Logo 应用领域
亚德诺 - ADI 传感器温度传感器
页数 文件大小 规格书
44页 1873K
描述
SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC

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ADT7519ARQ-REEL7 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：MO-137AB, QSOP-16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8最大精度（摄氏度）：1 Cel
主体宽度：3.91 mm主体高度：1.54 mm
主体长度或直径：4.9 mm外壳：PLASTIC
JESD-609代码：e0安装特点：SURFACE MOUNT
位数：8端子数量：16
最大工作电流：0.001 mA最高工作温度：120 °C
最低工作温度：-40 °C输出接口类型：4-WIRE INTERFACE
封装主体材料：PLASTIC/EPOXY封装等效代码：SSOP16,.25
封装形状/形式：RECTANGULAR电源：3/5 V
传感器/换能器类型：TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL子类别：Other Sensors
最大供电电压：5.5 V最小供电电压：2.7 V
表面贴装：YES技术：CMOS
温度系数：NEGATIVE ppm/ °C端子面层：Tin/Lead (Sn85Pb15)
端接类型：SOLDERBase Number Matches：1

ADT7519ARQ-REEL7 数据手册

 浏览型号ADT7519ARQ-REEL7的Datasheet PDF文件第3页浏览型号ADT7519ARQ-REEL7的Datasheet PDF文件第4页浏览型号ADT7519ARQ-REEL7的Datasheet PDF文件第5页浏览型号ADT7519ARQ-REEL7的Datasheet PDF文件第7页浏览型号ADT7519ARQ-REEL7的Datasheet PDF文件第8页浏览型号ADT7519ARQ-REEL7的Datasheet PDF文件第9页 
ADT7516/ADT7517/ADT7519  
Parameter1  
Min  
Typ  
Max  
Unit  
Conditions/Comments  
POWER REQUIREMENTS  
VDD  
VDD Settling Time  
IDD (Normal Mode)11  
2.7  
5.5  
50  
3
V
ms  
mA  
mA  
µA  
µA  
mW  
µW  
VDD settles to within 10% of its final voltage level.  
VDD = 3.3 V, VIH = VDD, and VIL = GND.  
VDD = 5 V, VIH = VDD, and VIL = GND.  
VDD = 3.3 V, VIH = VDD, and VIL = GND.  
VDD = 5 V, VIH = VDD, and VIL = GND.  
VDD = 3.3 V. Normal mode.  
2.2  
3
IDD (Power-Down Mode)  
Power Dissipation  
10  
10  
10  
33  
VDD = 3.3 V. Shutdown mode.  
1 See the Terminology section.  
2 DC specifications are tested with the outputs unloaded.  
3 Linearity is tested using a reduced code range: ADT7516 (Code 115 to 4095); ADT7517 (Code 28 to 1023); ADT7519 (Code 8 to 255).  
4 Guaranteed by design and characterization, not production tested.  
5 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.  
6 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (VREF = VDD), the offset  
plus gain error must be positive.  
7 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate  
but has a negative effect on the EMC behavior of the part.  
8 Guaranteed by design, not production tested.  
9 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.  
10 Measured with the load circuit shown in Figure 4.  
11 The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.  
DAC AC CHARACTERISTICS  
Table 2. VDD = 2.7 V to 5.5 V, RL = 4.7 kΩ to GND; CL = 200 pF to GND; 4.7 kΩ to VDD; all specifications TMIN to TMAX, unless  
otherwise noted.  
Parameter1, 2  
Min  
Typ3  
Max  
Unit  
Conditions/Comments  
Output Voltage Settling Time  
ADT7519  
ADT7517  
VREF = VDD = 5 V.  
6
7
8
8
9
10  
µs  
µs  
µs  
1/4 scale to 3/4 scale change (40h to C0h).  
1/4 scale to 3/4 scale change (100h to 300h).  
1/4 scale to 3/4 scale change (400h to C00h).  
ADT7516  
Slew Rate  
0.7  
12  
0.5  
1
0.5  
3
V/µs  
nV-s  
nV-s  
nV-s  
nV-s  
nV-s  
kHz  
dB  
Major-Code Change Glitch Energy  
Digital Feedthrough  
Digital Crosstalk  
Analog Crosstalk  
DAC-to-DAC Crosstalk  
Multiplying Bandwidth  
Total Harmonic Distortion  
1 LSB change around major carry.  
200  
–70  
VREF = 2 V 0.1 V p-p.  
VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz.  
1 See Terminology section.  
2 Guaranteed by design and characterization, not production tested.  
3 @ 25°C.  
t1  
SCL  
t5  
t2  
t4  
SDA  
DATA IN  
t3  
SDA  
DATA OUT  
t6  
Figure 2. I2C Bus Timing Diagram  
Rev. A | Page 6 of 44  
 
 
 
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