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ADT7490ARQZ

更新时间： 2024-02-14 06:54:07
品牌 Logo 应用领域
亚德诺 - ADI 模拟IC风扇信号电路光电二极管监控控制器
页数 文件大小 规格书
76页 1623K
描述
dBCool Remote Thermal Monitor and Fan Controller with PECI Interface

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ADT7490ARQZ 技术参数

是否Rohs认证：符合生命周期：Transferred
零件包装代码：SSOP包装说明：SSOP, SSOP24,.24
针数：24Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.04Is Samacsys：N
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：8.6614 mm
功能数量：1端子数量：24
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP24,.24封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.7526 mm子类别：Motion Control Electronics
最大供电电流 (Isup)：5 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9116 mmBase Number Matches：1

ADT7490ARQZ 数据手册

 浏览型号ADT7490ARQZ的Datasheet PDF文件第68页浏览型号ADT7490ARQZ的Datasheet PDF文件第69页浏览型号ADT7490ARQZ的Datasheet PDF文件第70页浏览型号ADT7490ARQZ的Datasheet PDF文件第72页浏览型号ADT7490ARQZ的Datasheet PDF文件第73页浏览型号ADT7490ARQZ的Datasheet PDF文件第74页 
ADT7490  
Table 78. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00)  
Bit No.  
Mnemonic  
R/W  
Description  
[7:0]  
Reserved  
Read-only  
Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and  
should not be written to under normal operation.  
Table 79. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00)  
Bit No.  
Mnemonic  
R/W  
Description  
[7:0]  
Reserved  
Read-only  
Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and  
should not be written to under normal operation.  
Table 80. Register 0x80—GPIO Configuration Register (Power-On Default = 0x00)  
Bit No. Mnemonic R/W  
Description  
[1:0]  
[2]  
RES  
GPIO2  
Reserved  
R/W  
Reserved.  
If GPIO2 is set to input, this register reflects the state of the pin. If GPIO2 is configured as an output,  
writing to this register asserts the output high or low depending on the polarity.  
[3]  
GPIO1  
R/W  
If GPIO1 is set to input, this register reflects the state of the pin. If GPIO1 is configured as an output,  
writing to this register asserts the output high or low depending on the polarity.  
[4]  
[5]  
[6]  
[7]  
GPIO2 POL R/W  
GPIO1 POL R/W  
GPIO2 polarity bit. Set to 0 for active low. Set to 1 for active high.  
GPIO1 polarity bit. Set to 0 for active low. Set to 1 for active high.  
GPIO2 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO2 to act as an output.  
GPIO1 direction bit. Set to 1 for GPIO1 to act as an input, set to 0 for GPIO1 to act as an output.  
GPIO2 DIR  
GPIO1 DIR  
R/W  
R/W  
Table 81. Register 0x81—Interrupt Status Register 4 (Power-On Default = 0x00)  
Bit No. Mnemonic R/W  
Description  
[2:0]  
[3]  
RES  
PECI1  
Read-only  
Read-only  
Reserved.  
A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client  
Address 0x31. This bit is cleared on a read of the status register only if the error condition has subsided.  
[4]  
[5]  
[6]  
[7]  
PECI2  
PECI3  
IMON  
Read-only  
Read-only  
Read-only  
Read-only  
A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client  
Address 0x32. This bit is cleared on a read of the status register only if the error condition has subsided.  
A Logic 1 indicates that the PECI high or low limit has been exceeded by the PECI value from PECI Client  
Address 0x33. This bit is cleared on a read of the status register only if the error condition has subsided.  
A Logic 1 indicates that the IMON high or low limit has been exceeded. This bit is cleared on a read of the  
status register only if the error condition has subsided.  
A Logic 1 indicates that the VTT high or low limit has been exceeded. This bit is cleared on a read of the  
status register only if the error condition has subsided.  
VTT  
Table 82. Register 0x82—Interrupt Mask Register 3 (Power-On Default = 0x00)1  
Bit No. Mnemonic R/W  
Description  
[0]  
PECI0  
DATA  
COMM  
OVT  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
A Logic 1 masks SMBALERT assertions for out-of-limit conditions on PECI0.  
A Logic 1 masks SMBALERT assertions for PECI data errors.  
A Logic 1 masks SMBALERT assertions for PECI communications errors.  
OVT = 1 masks SMBALERT for overtemperature THERM conditions.  
Reserved.  
[1]  
[2]  
[3]  
[6:4]  
[7]  
RES  
OOL  
OOL = 1 masks SMBALERT assertions when the OOL status bit is set.  
Note that the OOL mask bit is independent of the individual mask bits of Interrupt Mask 4 register  
(0x83). Therefore, if the intention is to mask SMBALERT assertions for any of the Status Register 4 bits,  
OOL must also be masked.  
1
SMBALERT  
If the mask bits in Register 0x82 are set, it is also necessary to set the OOL mask bit in Register 0x75 to ensure the  
output is not asserted.  
Rev. 0 | Page 71 of 76  
1...68697071727374...76

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