ADSP-2104/ADSP-2109
T he interrupt control register, ICNT L, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNT L, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
T he ADSP-2104/ADSP-2109 also provides either: one external
interrupt (IRQ2) and two serial ports (SPORT 0, SPORT 1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT 0).
The interrupt force and clear register, IFC, is a write-only register
that contains a force bit and a clear bit for each interrupt.
Clock Signals
T he ADSP-2104/ADSP-2109’s CLKIN input may be driven by
a crystal or by a T T L-compatible external clock signal. T he
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
When responding to an interrupt, the AST AT , MST AT , and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
T he status stack is seven levels deep to allow interrupt nesting.
T he stack is automatically popped when a return from the
interrupt instruction is executed.
If an external clock is used, it should be a T T L-compatible
signal running at the instruction rate. T he signal should be
connected to the processor’s CLKIN input; in this case, the
XT AL input must be left unconnected.
P in D efinitions
T able II shows pin definitions for the ADSP-2104/ADSP-2109
Because the processor includes an on-chip oscillator circuit, an
external crystal may also be used. T he crystal should be con-
nected across the CLKIN and XT AL pins, with two capacitors
connected as shown in Figure 2. A parallel-resonant, fundamen-
tal frequency, microprocessor-grade crystal should be used.
processors. Any inputs not used must be tied to VDD
.
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-2104/ADSP-2109,
with two serial I/O devices, a boot EPROM, and optional external
program and data memory. A total of 14.25K words of data
memory and 14.5K words of program memory is addressable.
Table II. AD SP -2104/AD SP -2109 P in D efinitions
P in
Nam e(s)
# of
P ins
Input /
O utput
Function
Address
Data1
14
24
O
I/O
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request # 2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
RESET
IRQ2
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
BR2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XT AL
CLKOUT
VDD
I
O
GND
Ground Pins
SPORT 0
SPORT 1
or Interrupts & Flags:
IRQ0 (RFS1)
IRQ1 (TFS1)
FI (DR1)
FO (DT1)
5
5
I/O
I/O
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
1
1
1
1
I
I
I
O
External Interrupt Request # 0
External Interrupt Request # 1
Flag Input Pin
Flag Output Pin
NOT ES
1Unused data bus lines may be left floating.
2BR must be tied high (to VDD) if not used.
REV. 0
–5–
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