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ADSP-BF525KBCZ-6C2 PDF预览

ADSP-BF525KBCZ-6C2

更新时间: 2024-02-24 06:31:34
品牌 Logo 应用领域
亚德诺 - ADI 外围集成电路
页数 文件大小 规格书
36页 910K
描述
Low Power Blackfin Processor with Advanced Peripherals and Embedded Stereo Audio CODEC

ADSP-BF525KBCZ-6C2 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:LFBGA, BGA289,23X23,20针数:289
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:2.31
桶式移位器:NO位大小:32
边界扫描:YES格式:FIXED POINT
内部总线架构:SINGLEJESD-30 代码:S-PBGA-B289
JESD-609代码:e1长度:12 mm
低功率模式:YES湿度敏感等级:3
端子数量:289最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA289,23X23,20
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.4 mm
速度:600 MHz子类别:Microprocessors
最大供电电压:3.6 V最小供电电压:1.8 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:12 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADSP-BF525KBCZ-6C2 数据手册

 浏览型号ADSP-BF525KBCZ-6C2的Datasheet PDF文件第5页浏览型号ADSP-BF525KBCZ-6C2的Datasheet PDF文件第6页浏览型号ADSP-BF525KBCZ-6C2的Datasheet PDF文件第7页浏览型号ADSP-BF525KBCZ-6C2的Datasheet PDF文件第9页浏览型号ADSP-BF525KBCZ-6C2的Datasheet PDF文件第10页浏览型号ADSP-BF525KBCZ-6C2的Datasheet PDF文件第11页 
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C  
Recording Mode  
The digital audio interface sends the ADC digital filter data to  
the ADCDAT output pin for recording. The ADCDAT data  
stream multiplexes the left- and right-channel audio data in the  
time domain. The ADCLRC clock signal separates left- and  
right-channel digital audio frames on the ADCDAT lines.  
The CODEC_BCLK signal clocks the digital audio data within  
the frames. The CODEC_BCLK signal is either an input or an  
output depending on whether the codec is in master or slave  
mode. During a recording operation, ADCDAT and ADCLRC  
must be synchronous to the CODEC_BCLK signal to avoid data  
corruption.  
Playback Mode  
The digital audio interface receives data on the DACDAT input  
pin for playback. The digital audio data stream on the DACDAT  
pin is time-domain-multiplexed left and right channel audio  
data. The DACLRC clock signal separates left and right channel  
digital audio frames on the DACDAT lines.  
The CODEC_BCLK signal clocks the digital audio data within  
the frames. The CODEC_BCLK signal is either an input or an  
output depending on whether the codec is in master or slave  
mode. During a playback operation, DACDAT and DACLRC  
must be synchronous to the CODEC_BCLK signal to avoid data  
corruption.  
Digital Audio Data Sampling Rate  
To accommodate a wide variety of commonly used DAC and  
ADC sampling rates, the codec allows for two modes of opera-  
tion, normal and USB, selected by the USB bit (Register R8,  
Bit D0).  
The sampling rate is generated as a fixed divider from the  
CODEC_MCLK signal. Because all audio processing references  
the CODEC_MCLK signal, corruption of this signal will corrupt  
the quality of the audio at the codec output. The ADCLRC/  
ADCDAT/CODEC_BCLK or DACLRC/DACDAT/  
CODEC_BCLK signals must be synchronized with  
CODEC_MCLK in the digital audio interface circuit.  
CODEC_MCLK must be faster or equal to the CODEC_BCLK  
frequency to guarantee that no data is lost during data synchro-  
nization. The CODEC_BCLK frequency should be greater than  
the sampling rate × word length × 2. Ensuring that the  
CODEC_BCLK frequency is greater than this, guarantees that  
all valid data bits are captured by the digital audio interface cir-  
cuitry. For example, if a 32 kHz digital audio sampling rate with  
a 32-bit word length is desired, CODEC_BCLK = 2.048 MHz.  
Rev. A  
| Page 8 of 36 | March 2010  

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