ADSP-2183
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock, and thus its response time, to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-2183 will remain in the
idle state for up to a maximum of n processor cycles (n = 16, 32,
64 or 128) before resuming normal operation.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2183 uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
When the IDLE (n) instruction is used in systems with an exter-
nally generated serial clock (SCLK), the serial clock rate may be
faster than the processor’s reduced internal clock rate. Under
these conditions, interrupts must not be generated at a faster
rate than can be serviced, due to the additional time the processor
takes to come out of the idle state (a maximum of n processor
cycles).
Because the ADSP-2183 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
SYSTEM INTERFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2183, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories. Program-
mable wait state generation allows the processor to connect
easily to slow peripheral devices. The ADSP-2183 also provides
four external interrupts and two serial ports or six external inter-
rupts and one serial port.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
ADSP-2183
XTAL
CLKIN
DSP
CLKOUT
1/2x CLOCK
OR
CLKIN
XTAL
A
14
13-0
ADDR13-0
CRYSTAL
A0-A21
D
23-16
FL0-2
PF0-7
BYTE
D
15-8
24
MEMORY
DATA23-0
DATA
IRQ2
BMS
CS
IRQE
IRQL0
IRQL1
Figure 3. External Crystal Connections
A
D
10-0
ADDR
DATA
Reset
23-8
RD
WR
I/O
SPACE
SPORT1
The RESET signal initiates a master reset of the ADSP-2183.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
SCLK1
RFS1 OR IRQ0
(PERIPHERALS)
SERIAL
DEVICE
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
IOMS
CS
2048 LOCATIONS
A
13-0
SPORT0
SCLK0
RFS0
ADDR
DATA
OVERLAY
MEMORY
D
23-0
SERIAL
DEVICE
TFS0
TWO 8K
PMS
DMS
CMS
DT0
PM SEGMENTS
DR0
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
TWO 8K
IDMA PORT
DM SEGMENTS
BR
BG
BGH
IRD
IWR
IS
IAL
IACK
SYSTEM
INTERFACE
OR
PWD
CONTROLLER
16
PWDACK
IAD15-0
Figure 2. ADSP-2183 Basic System Configuration
Clock Signals
mum pulsewidth specification, tRSP
.
The ADSP-2183 can be clocked by either a crystal or a TTL-
compatible clock signal.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
–6–
REV. C
5秒后页面跳转
TLP250光耦合器：资料手册参数分析
DA14580 低功耗蓝牙系统级芯片(SoC)：资料手册参数分析
INA226 高精度电流和功率监控器：资料手册参数分析
SI2302 N沟道MOSFET：资料手册参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
