ADSP-2183
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
#
of
Pins
Pin
Name(s)
Input/
Output Function
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
CLKOUT
SPORT0
SPORT1
1
5
5
O
I/O
I/O
Processor Clock Output.
Serial Port I/O Pins
Serial Port 1 or Two External
IRQs, Flag In and Flag Out
IDMA Port Read/Write Inputs
IDMA Port Select
IDMA Port Address Latch
Enable
IDMA Port Address/Data Bus
IDMA Port Access Ready
Acknowledge
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
IRD, IWR
IS
2
1
1
I
I
I
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
IAL
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
IAD
IACK
16
1
I/O
O
PWD
1
1
I
O
Power-Down Control
Power-Down Control
Pin Descriptions
The ADSP-2183 is available in a 128-lead LQFP package, and
Mini-BGA.
PWDACK
FL0, FL1,
FL2
PF7:0
EE
EBR
3
8
1
1
1
1
1
1
1
1
1
11
6
O
I/O
*
*
*
*
*
*
*
Output Flags
Programmable I/O Pins
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
Ground Pins (LQFP)
Power Supply Pins (LQFP)
Ground Pins (Mini-BGA)
Power Supply Pins (Mini-BGA)
PIN FUNCTION DESCRIPTIONS
#
of
Pin
Input/
Output Function
Name(s)
Pins
EBG
Address
14
O
Address Output Pins for Program,
Data, Byte, & I/O Spaces
Data I/O Pins for Program and
Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)
Processor Reset Input
Edge- or Level-Sensitive
Interrupt Request
ERESET
EMS
Data
24
I/O
EINT
ECLK
ELIN
ELOUT
GND
VDD
GND
VDD
*
*
RESET
IRQ2
1
1
I
I
IRQL0,
IRQL1
22
11
2
1
I
I
Level-Sensitive Interrupt
Requests
Edge-Sensitive Interrupt
Request
*These ADSP-2183 pins must be connected only to the EZ-ICE connector in
the target system. These pins have no function except during emulation, and
do not require pull-up or pull-down resistors.
IRQE
BR
1
1
1
1
1
1
1
1
1
1
1
1
I
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Interrupts
BG
O
O
O
O
O
O
O
O
O
I
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2183 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP-
2183 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power-down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
BGH
PMS
DMS
BMS
IOMS
CMS
RD
Program Memory Select Output
Data Memory Select Output
Byte Memory Select Output
I/O Space Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Memory Map Select Input
Boot Option Control Input
WR
MMAP
BMODE
CLKIN,
XTAL
I
2
I
Clock or Quartz Crystal Input
–4–
REV. C
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