ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
GENERAL DESCRIPTION
The ADSP-2148x SHARC® processors are members of the
SIMD SHARC family of DSPs that feature Analog Devices’
Super Harvard Architecture. The processors are source code
compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,
ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as
with first generation ADSP-2106x SHARC processors in SISD
(single-instruction, single-data) mode. The ADSP-2148x pro-
cessors are 32-bit/40-bit floating point processors optimized for
high performance audio applications with large on-chip SRAM,
multiple internal buses to eliminate I/O bottlenecks, and an
innovative digital applications interface (DAI).
Table 1. Processor Benchmarks
Speed
Speed
(at 400 MHz) (at 450 MHz)
Benchmark Algorithm
1024 Point Complex FFT
(Radix 4, with Reversal)
23 μs
20.44 μs
FIR Filter (per Tap)1
IIR Filter (per Biquad)1
1.25 ns
5 ns
1.1 ns
4.43 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
11.25 ns
20 ns
10.0 ns
17.78 ns
Table 1 shows performance benchmarks for the ADSP-2148x
processors. Table 2 shows the features of the individual product
offerings.
Divide (y/×)
7.5 ns
6.67 ns
10.0 ns
Inverse Square Root
1 Assumes two files in multichannel SIMD mode
11.25 ns
Table 2. ADSP-2148x Family Features
Feature
ADSP-21483 ADSP-21486
ADSP-21487
ADSP-21488
400 MHz
2/3 Mbits1
ADSP-21489
450 MHz
Maximum Instruction Rate
RAM
400 MHz
3 Mbits
400 MHz
450 MHz
5 Mbits
5 Mbits
ROM
4 Mbits
No
No
Audio Decoders in ROM2
Pulse-Width Modulation
DTCP Hardware Accelerator
Yes
4 Units (3 Units on 100-Lead Packages)
Contact Analog Devices
External Port Interface (SDRAM, AMI)3 Yes (16-bit)
AMI Only
Yes (16-bit)
Serial Ports
8
Direct DMA from SPORTs to
Yes
External Port (External Memory)
FIR, IIR, FFT Accelerator
Watchdog Timer
MediaLB Interface
IDP/PDAP
Yes
Yes (176-Lead Package Only)
Automotive Models Only
Yes
1
UART
DAI (SRU)/DPI (SRU2)
S/PDIF Transceiver
SPI
Yes
Yes
Yes
TWI
1
SRC Performance4
Thermal Diode
VISA Support
–128 dB
Yes
Yes
Package3
176-Lead LQFP EPAD
100-Lead LQFP EPAD
176-Lead LQFP EPAD 176-Lead LQFP EPAD 176-Lead LQFP EPAD
88-Lead LFCSP5 100-Lead LQFP EPAD 100-Lead LQFP EPAD5
88-Lead LFCSP5 88-Lead LFCSP5
1 See Ordering Guide on Page 70.
2 ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm
combination support varies depending upon the chip version and the system configurations. Visit www.analog.com for complete information.
3 The 100-lead and 88-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin
FunctionDescriptionsonPage 14. TheADSP-21486 processorin the176-leadpackagealso does notcontaina SDRAMcontroller. Formoreinformation, see176-LeadLQFP_EP
Lead Assignment on page 62.
4 Some models have –140 dB performance. For more information, see Ordering Guide on page 70.
5 Only available up to 400 MHz. See Ordering Guide on Page 70 for details.
Rev. H
| Page 3 of 71 | February 2020
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