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ADSP-21371KSWZ-2A PDF预览

ADSP-21371KSWZ-2A

更新时间: 2024-01-04 10:41:08
品牌 Logo 应用领域
亚德诺 - ADI 时钟外围集成电路
页数 文件大小 规格书
56页 1121K
描述
32-BIT, 16.67MHz, OTHER DSP, PQFP208, ROHS COMPLIANT, MS-026BJB-HD, LQFP-208

ADSP-21371KSWZ-2A 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:HLFQFP, QFP208,1.2SQ,20针数:208
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.6
地址总线宽度:24桶式移位器:YES
位大小:32边界扫描:YES
最大时钟频率:16.67 MHz外部数据总线宽度:32
格式:FLOATING POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PQFP-G208JESD-609代码:e3
长度:28 mm低功率模式:NO
湿度敏感等级:3端子数量:208
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.2,3.3 V认证状态:Not Qualified
RAM(字数):32768座面最大高度:1.6 mm
子类别:Digital Signal Processors最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:28 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

ADSP-21371KSWZ-2A 数据手册

 浏览型号ADSP-21371KSWZ-2A的Datasheet PDF文件第1页浏览型号ADSP-21371KSWZ-2A的Datasheet PDF文件第2页浏览型号ADSP-21371KSWZ-2A的Datasheet PDF文件第4页浏览型号ADSP-21371KSWZ-2A的Datasheet PDF文件第5页浏览型号ADSP-21371KSWZ-2A的Datasheet PDF文件第6页浏览型号ADSP-21371KSWZ-2A的Datasheet PDF文件第7页 
ADSP-21371/ADSP-21375  
GENERAL DESCRIPTION  
The ADSP-21371/ADSP-21375 SHARC® processors are mem-  
bers of the SIMD SHARC family of DSPs that feature Analog  
Devices’ Super Harvard Architecture. The processors are source  
code compatible with the ADSP-2126x, ADSP-2136x, and  
ADSP-2116x DSPs, as well as with first generation ADSP-2106x  
SHARC processors in SISD (single-instruction, single-data)  
mode. The processors are 32-bit/40-bit floating-point proces-  
sors optimized for high performance automotive audio  
applications with their large on-chip SRAM and mask-pro-  
grammable ROM, multiple internal buses to eliminate I/O  
bottlenecks, and an innovative digital applications interface  
(DAI).  
Table 2. ADSP-21371/ADSP-21375 Features (Continued)  
Feature  
ADSP-21371  
ADSP-21375  
Yes  
Digital Peripheral Interface  
(DPI)  
S/PDIF Transceiver  
Yes  
No  
SPI  
2
TWI  
Yes  
208-Lead LQFP_EP  
Package  
As shown in the functional block diagram on Page 1, the pro-  
cessors use two computational units to deliver a significant  
performance increase over the previous SHARC processors on a  
range of DSP algorithms. Fabricated in a state-of-the-art, high  
speed, CMOS process, the processors achieve an instruction  
cycle time of 3.75 ns at 266 MHz. With its SIMD computational  
hardware, the processors can perform 1.596 GFLOPS running  
at 266 MHz.  
The diagram on Page 1 shows the two clock domains that make  
up the ADSP-2137x processors. The core clock domain contains  
the following features:  
• Two processing elements, each of which comprises an  
ALU, multiplier, shifter, and data register file  
• Data address generators (DAG1, DAG2)  
• Program sequencer with instruction cache  
Table 1 shows performance benchmarks for these devices.  
Table 2 shows the features of the individual product offerings.  
• PM and DM buses capable of supporting four 32-bit data  
transfers between memory and the core at every core pro-  
cessor cycle  
Table 1. Processor Benchmarks (at 266 MHz)  
• One periodic interval timer with pinout  
Speed  
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,  
ADSP-21375)  
Benchmark Algorithm  
(at 266 MHz)  
1024 Point Complex FFT (Radix 4, With Reversal) 34.5 s  
• On-chip mask-programmable ROM (4M bit, ADSP-21371;  
2M bit, ADSP-21375)  
FIR Filter (per Tap)1  
IIR Filter (per Biquad)1  
1.88 ns  
7.5 ns  
• JTAG test access port for emulation and boundary scan.  
The JTAG provides software debug through user break-  
points which allow flexible exception handling.  
Matrix Multiply (Pipelined)  
[3 × 3] × [3 × 1]  
[4 × 4] × [4 × 1]  
16.91 ns  
30.07 ns  
The diagram on Page 1 also shows the peripheral clock domains  
(also known as the I/O processor) and contains the following  
features:  
Divide (y/x)  
13.1 ns  
20.4 ns  
Inverse Square Root  
1 Assumes two files in multichannel SIMD mode  
• IOD0 (peripheral DMA) and IOD1 (external port DMA)  
buses for 32-bit data transfers  
Table 2. ADSP-21371/ADSP-21375 Features  
• Peripheral and external port bus for core connection  
• Digital applications interface that includes four precision  
clock generators (PCG), an S/PDIF-compatible digital  
audio receiver/transmitter, an input data port (IDP), eight  
serial ports, eight serial interfaces, a 20-bit parallel input  
port (PDAP), and a flexible signal routing unit (DAI SRU).  
Feature  
ADSP-21371  
ADSP-21375  
Frequency  
266 MHz  
(3.75 ns)  
266 MHz  
(3.75 ns)  
RAM  
1M bit  
4M bits  
Yes  
0.5M bit  
2M bits  
No  
• Digital peripheral interface that includes two timers, one  
UART, two serial peripheral interfaces (SPI), a 2-wire  
interface (TWI), and a flexible signal routing unit  
(DPI SRU).  
ROM  
Pulse-Width Modulation  
Serial Ports  
8
4
• External port with AMI and SDRAM controller  
• Four units for PWM control  
UART  
1
Digital Application  
Interface (DAI)  
Yes  
• One MTM for internal to internal memory transfers  
Rev. D  
| Page 3 of 56 | April 2013  
 

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