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ADSP-21371BSWZ-2B PDF预览

ADSP-21371BSWZ-2B

更新时间: 2024-02-04 06:22:33
品牌 Logo 应用领域
亚德诺 - ADI 时钟外围集成电路
页数 文件大小 规格书
56页 1121K
描述
High-Performance 32-bit Floating-Point SHARC Processor for Automotive Audio

ADSP-21371BSWZ-2B 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:HLFQFP, QFP208,1.2SQ,20针数:208
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:2.26
地址总线宽度:24桶式移位器:YES
位大小:32边界扫描:YES
最大时钟频率:16.67 MHz外部数据总线宽度:32
格式:FLOATING POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PQFP-G208JESD-609代码:e3
长度:28 mm低功率模式:NO
湿度敏感等级:3端子数量:208
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):250
电源:1.2,3.3 V认证状态:Not Qualified
RAM(字数):32768座面最大高度:1.6 mm
子类别:Digital Signal Processors最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:28 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

ADSP-21371BSWZ-2B 数据手册

 浏览型号ADSP-21371BSWZ-2B的Datasheet PDF文件第1页浏览型号ADSP-21371BSWZ-2B的Datasheet PDF文件第2页浏览型号ADSP-21371BSWZ-2B的Datasheet PDF文件第3页浏览型号ADSP-21371BSWZ-2B的Datasheet PDF文件第5页浏览型号ADSP-21371BSWZ-2B的Datasheet PDF文件第6页浏览型号ADSP-21371BSWZ-2B的Datasheet PDF文件第7页 
ADSP-21371/ADSP-21375  
Entering SIMD mode also has an effect on the way data is trans-  
ferred between memory and the processing elements. When in  
SIMD mode, twice the data bandwidth is required to sustain  
computational operation in the processing elements. Because of  
this requirement, entering SIMD mode also doubles the band-  
width between memory and the processing elements. When  
using the DAGs to transfer data in SIMD mode, two data values  
are transferred with each access of memory or the register file.  
SHARC FAMILY CORE ARCHITECTURE  
The ADSP-21371/ADSP-21375 processors are code compatible  
at the assembly level with the ADSP-2136x, ADSP-2126x,  
ADSP-21160x, and ADSP-21161N, and with the first generation  
ADSP-2106x SHARC processors. The ADSP-21371/  
ADSP-21375 processors share architectural features with the  
ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC  
processors, as shown in Figure 2 and detailed in the following  
sections.  
Independent, Parallel Computation Units  
Within each processing element is a set of computational units.  
The computational units consist of an arithmetic/logic unit  
(ALU), multiplier, and shifter. These units perform all opera-  
tions in a single cycle. The three units within each processing  
element are arranged in parallel, maximizing computational  
throughput. Single multifunction instructions execute parallel  
ALU and multiplier operations. In SIMD mode, the parallel  
ALU and multiplier operations occur in both processing ele-  
ments. These computation units support IEEE 32-bit single-  
precision floating-point, 40-bit extended precision floating-  
point, and 32-bit fixed-point data formats.  
SIMD Computational Engine  
The processors contain two computational processing elements  
that operate as a single-instruction, multiple-data (SIMD)  
engine. The processing elements are referred to as PEX and  
PEY, and each contains an ALU, multiplier, shifter, and register  
file. PEX is always active, and PEY may be enabled by setting the  
PEYEN mode bit in the MODE1 register. When this mode is  
enabled, the same instruction is executed in both processing ele-  
ments, but each processing element operates on different data.  
This architecture is efficient at executing math intensive DSP  
algorithms.  
S
JTAG  
FLAG TIMER INTERRUPT CACHE  
SIMD Core  
PM ADDRESS 24  
DMD/PMD 64  
5 STAGE  
PROGRAM SEQUENCER  
PM DATA 48  
DAG2  
16x32  
DAG1  
16x32  
PM ADDRESS 32  
SYSTEM  
I/F  
DM ADDRESS 32  
PM DATA 64  
USTAT  
4x32-BIT  
PX  
64-BIT  
DM DATA 64  
DATA  
SWAP  
RF  
Rx/Fx  
PEx  
RF  
Sx/SFx  
PEy  
ALU  
SHIFTER  
MULTIPLIER  
MULTIPLIER  
ALU  
SHIFTER  
16x40-BIT  
16x40-BIT  
MRB  
80-BIT  
MSB  
80-BIT  
MRF  
80-BIT  
MSF  
80-BIT  
ASTATy  
STYKy  
ASTATx  
STYKx  
Figure 2. SHARC Core Block Diagram  
Rev. D  
| Page 4 of 56 | April 2013  
 

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