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ADSP-21366SKBCZENG PDF预览

ADSP-21366SKBCZENG

更新时间: 2024-02-23 17:31:26
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
54页 523K
描述
SHARC Processor

ADSP-21366SKBCZENG 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LEAD FREE, MS-026BFB-HD, HSLQFP-144针数:144
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.84
其他特性:ALSO REQUIRES 3.3V SUPPLY地址总线宽度:16
桶式移位器:YES边界扫描:YES
最大时钟频率:55.55 MHz外部数据总线宽度:16
格式:FLOATING POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PQFP-G144长度:20 mm
低功率模式:NO端子数量:144
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:20 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADSP-21366SKBCZENG 数据手册

 浏览型号ADSP-21366SKBCZENG的Datasheet PDF文件第1页浏览型号ADSP-21366SKBCZENG的Datasheet PDF文件第2页浏览型号ADSP-21366SKBCZENG的Datasheet PDF文件第3页浏览型号ADSP-21366SKBCZENG的Datasheet PDF文件第5页浏览型号ADSP-21366SKBCZENG的Datasheet PDF文件第6页浏览型号ADSP-21366SKBCZENG的Datasheet PDF文件第7页 
ADSP-21365/6  
Preliminary Technical Data  
ADSP-21365/6  
CLKOUT  
CLKIN  
X TAL  
CLOCK  
ALE  
2
LATCH  
AD1 5-0  
ADDR  
CLK_CFG1-0  
BOOTCFG1-0  
FLAG3-1  
PARALLEL  
PORT  
RAM, ROM  
BOO T ROM  
I/O DEVICE  
2
3
DATA  
OE  
RD  
WR  
WE  
FLAG0  
CS  
ADC  
(OPTIONAL)  
CLK  
FS  
S DAT  
DAI_P1  
DAI_ P2  
DAI_ P3  
S CLK0  
S FS0  
S D0A  
S D0B  
SRU  
DAC  
(OPTIONAL)  
CLK  
DAI_P 18  
DAI_P 19  
DAI_ P2 0  
SP ORT0-5  
TIME RS  
FS  
S DAT  
SPDIF  
SRC  
IDP  
S PI  
CLK  
FS  
PCGA  
P CG B  
DAI  
RES ET  
JTAG  
6
Figure 2. ADSP-21365/6 System Sample Configuration  
Independent, Parallel Computation Units  
Single-Cycle Fetch of Instruction and Four Operands  
Within each processing element is a set of computational units.  
The computational units consist of an arithmetic/logic unit  
(ALU), multiplier, and shifter. These units perform all opera-  
tions in a single cycle. The three units within each processing  
element are arranged in parallel, maximizing computational  
throughput. Single multifunction instructions execute parallel  
ALU and multiplier operations. In SIMD mode, the parallel  
ALU and multiplier operations occur in both processing ele-  
ments. These computation units support IEEE 32-bit single-  
precision floating-point, 40-bit extended precision floating-  
point, and 32-bit fixed-point data formats.  
The ADSP-21365/6 features an enhanced Harvard architecture  
in which the data memory (DM) bus transfers data and the pro-  
gram memory (PM) bus transfers both instructions and data  
(see Figure 1 on page 1). With the ADSP-21365/6’s separate  
program and data memory buses and on-chip instruction cache,  
the processor can simultaneously fetch four operands (two over  
each data bus) and one instruction (from the cache), all in a sin-  
gle cycle.  
Instruction Cache  
The ADSP-21365/6 includes an on-chip instruction cache that  
enables three-bus operation for fetching an instruction and four  
data values. The cache is selective—only the instructions whose  
fetches conflict with PM bus data accesses are cached. This  
cache allows full-speed execution of core, looped operations  
such as digital filter multiply-accumulates, and FFT butterfly  
processing.  
Data Register File  
A general-purpose data register file is contained in each pro-  
cessing element. The register files transfer data between the  
computation units and the data buses, and store intermediate  
results. These 10-port, 32-register (16 primary, 16 secondary)  
register files, combined with the ADSP-2136x enhanced Har-  
vard architecture, allow unconstrained data flow between  
computation units and internal memory. The registers in PEX  
are referred to as R0-R15 and in PEY as S0-S15.  
Data Address Generators With Zero-Overhead Hardware  
Circular Buffer Support  
The ADSP-21365/6’s two data address generators (DAGs) are  
used for indirect addressing and implementing circular data  
buffers in hardware. Circular buffers allow efficient program-  
ming of delay lines and other data structures required in digital  
Rev. PrA  
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Page 4 of 54  
|
September 2004  

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