ADSP-21365/6
Preliminary Technical Data
Up to 12 TDM stream support, each with 128 channels per
frame
KEY FEATURES – PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365/6
performs 2 GFLOPS/666 MMACS
3M bit on-chip SRAM (1M Bit in blocks 0 and 1, and 0.50M Bit
in blocks 2 and 3) for simultaneous access by the core pro-
cessor and DMA
4M bit on-chip mask-programmable ROM (2M bit in block 0
and 2M bit in block 1)
Dual Data Address Generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single Instruction Multiple Data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the pro-
cessor core, configurable as eight channels of serial data or
seven channels of serial data and a single channel of up to
a 20-bit wide parallel data
Signal routing unit provides configurable and flexible con-
nections between all DAI components–six serial ports, one
SPI port, eight channels of asynchronous sample rate con-
verters, an S/PDIF receiver/transmitter, DTCP (Digital
Content Transmission Protocol (ADSP-21365 only), three
timers, an SPI port,10 interrupts, six flag inputs, six flag
outputs, and 20 SRU I/O pins (DAI_Px)
Two Serial Peripheral Interfaces (SPI): primary on dedicated
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI , Full-
duplex operation, Master-Slave mode multi-master sup-
port, Open drain outputs, Programmable baud rates, clock
polarities and phases
Parallelism in busses and computational units allows sin-
gle cycle execution (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
DEDICATED AUDIO COMPONENTS
Transfers between memory and core at a sustained 5.4G
bytes/s bandwidth at 333 MHz core instruction rate
S/PDIF Compatible Digital Audio receiver/transmitter sup-
ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I2S or right-justified serial data input with
16, 18, 20 or 24-bit word widths (transmitter)
Two channel mode and Single Channel Double Frequency
(SCDF) mode
Digital Transmission Content Protection (DTCP)—a crypto-
graphic protocol for protecting audio content from
unauthorized copying, intercepting, and tampering
(ADSP-21365 only).
INPUT/OUTPUT FEATURES
DMA Controller supports:
25 DMA channels for transfers between ADSP-21365/6 inter-
nal memory and a variety of peripherals
32-bit DMA transfers at core clock speed, in parallel with full-
speed processor execution
Asynchronous parallel port provides access to asynchronous
external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
Sample Rate Converter (SRC) Contains a Serial Input Port, De-
emphasis Filter, Sample Rate Converter (SRC) and Serial
Output Port providing up to -128db SNR performance
Supports Left Justified, I2S, TDM and Right Justified 24, 20,
18 and 16-bit serial formats (input)
55M byte per sec transfer rate
External memory access in a dedicated DMA channel
8- to 32-bit and 16- to 32-bit packing options
Programmable data cycle duration: 2 to 31 CCLK
Digital Audio Interface (DAI) includes six serial ports, two
Precision Clock Generators, an Input Data Port, three tim-
ers, an S/PDIF transceiver, a DTCP cipher (ADSP-21365
only), an 8-channel asynchronous sample rate converter,
an SPI port, and a Signal Routing Unit
Six dual data line serial ports that operate at up to 50M bits/s
on each data line — each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair
Pulse Width Modulation provides:
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in non-paired mode
ROM Based Security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Left-justified Sample Pair and I2S Support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I2S compatible stereo devices per serial
port
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball Mini-BGA and 144-lead LQFP Packages
(see Ordering Guide on page 51)
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Rev. PrA
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Page 2 of 54
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September 2004
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