ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
audio channels in I2S, left-justified sample pair, or right-justi-
fied mode. One frame sync cycle indicates one 64-bit left/right
pair, but data is sent to the FIFO as 32-bit words (that is, one-
half of a frame at a time). The processor supports 24- and 32-bit
I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit
right-justified formats.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the processor boots at system power-up
from an 8-bit EPROM via the parallel port, an SPI master, an
SPI slave, or an internal boot. Booting is determined by the boot
configuration (BOOT_CFG1–0) pins in Table 5. Selection of the
boot source is controlled via the SPI as either a master or slave
device, or it can immediately begin executing from ROM.
Precision Clock Generator (PCG)
The precision clock generators (PCG) consist of two units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A and B, are identi-
cal in functionality and operate independently of each other.
The two signals generated by each unit are normally used as a
serial bit clock/frame sync pair.
Table 5. Boot Mode Selection
BOOT_CFG1–0
Booting Mode
Peripheral Timers
00
01
10
11
SPI Slave Boot
The following three general-purpose timers can generate peri-
odic interrupts and be independently set to operate in one of
three modes:
SPI Master Boot
Parallel Port Boot via EPROM
No booting occurs. Processor executes
from internal ROM after reset.
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
Phase-Locked Loop
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configu-
ration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables all three general-purpose timers
independently.
The processors use an on-chip phase-locked loop (PLL) to gen-
erate the internal clock for the core. On power-up, the
CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and
6:1. After booting, numerous other ratios can be selected via
software control.
The ratios are made up of software configurable numerator val-
ues from 1 to 64 and software configurable divisor values of 1, 2,
4, and 8.
I/O PROCESSOR FEATURES
The processor’s I/O provides many channels of DMA and con-
trols the extensive set of peripherals described in the previous
sections.
Power Supplies
The processor has a separate power supply connection for the
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS
)
DMA Controller
power supplies. The internal and analog supplies must meet the
1.2 V requirement for K, B, and Y grade models, and the 1.0 V
requirement for Y models. (For information on the temperature
ranges offered for this product, see Operating Conditions on
Page 14, Package Information on Page 16, and Ordering Guide
on Page 56.) The external supply must meet the 3.3 V require-
ment. All external supply pins must be connected to the same
power supply.
The processor’s on-chip DMA controllers allow data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the processor’s internal memory and its serial ports, the
SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP), or
the parallel port (PP). See Table 4.
Note that the analog supply pin (AVDD) powers the processor’s
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
Table 4. DMA Channels
A
VDD pin. Place the filter components as close as possible to the
Peripheral
SPORTs
ADSP-2136x
AVDD/AVSS pins. For an example circuit, see Figure 3. (A
recommended ferrite chip is the muRata BLM18AG102SN1D.)
To reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for VDDINT and GND. Use wide traces
12
8
IDP/PDAP
SPI
2
to connect the bypass capacitors to the analog power (AVDD
and ground (AVSS) pins. Note that the AVDD and AVSS pins
)
MTM/DTCP
Parallel Port
Total DMA Channels
2
1
specified in Figure 3 are inputs to the processor and not the ana-
log ground plane on the board—the AVSS pin should connect
directly to digital ground (GND) at the chip.
25
Rev. J
|
Page 8 of 60
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July 2013
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