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ADSP-21364SKBCZENG

更新时间： 2024-02-26 18:28:37
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
52页 487K
描述
SHARC Processor

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ADSP-21364SKBCZENG 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：MS-026BFB-HD, HSLQFP-144针数：144
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.78
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：16
桶式移位器：YES边界扫描：YES
最大时钟频率：55.55 MHz外部数据总线宽度：16
格式：FLOATING POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G144JESD-609代码：e0
长度：20 mm低功率模式：NO
端子数量：144最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：HLFQFP封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：1.26 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：20 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

ADSP-21364SKBCZENG 数据手册

 浏览型号ADSP-21364SKBCZENG的Datasheet PDF文件第1页浏览型号ADSP-21364SKBCZENG的Datasheet PDF文件第2页浏览型号ADSP-21364SKBCZENG的Datasheet PDF文件第3页浏览型号ADSP-21364SKBCZENG的Datasheet PDF文件第5页浏览型号ADSP-21364SKBCZENG的Datasheet PDF文件第6页浏览型号ADSP-21364SKBCZENG的Datasheet PDF文件第7页 
ADSP-21364  
Preliminary Technical Data  
ADSP-21364  
CLKOUT  
CLKIN  
XTAL  
CLOCK  
ALE  
2
LATCH  
AD1 5-0  
ADDR  
CLK_CFG1-0  
BOOTCFG1-0  
FLAG3-1  
PARALLEL  
PORT  
RAM, ROM  
BOO T ROM  
I/O DEVICE  
2
3
DATA  
OE  
RD  
WR  
WE  
FLAG0  
CS  
ADC  
(OPTIONAL)  
CLK  
FS  
SDAT  
DAI_P1  
DAI_ P2  
DAI_ P3  
SCLK0  
SFS0  
SD0A  
SD0B  
SRU  
DAC  
(OPTIONAL)  
CLK  
DAI_P18  
DAI_P19  
DAI_ P2 0  
SPORT0-5  
TIMERS  
SPDIF  
FS  
SDAT  
SRC  
IDP  
SPI  
CLK  
FS  
PCGA  
PCGB  
DAI  
RESET  
JTAG  
6
Figure 2. ADSP-21364 System Sample Configuration  
Independent, Parallel Computation Units  
Single-Cycle Fetch of Instruction and Four Operands  
Within each processing element is a set of computational units.  
The computational units consist of an arithmetic/logic unit  
(ALU), multiplier, and shifter. These units perform all opera-  
tions in a single cycle. The three units within each processing  
element are arranged in parallel, maximizing computational  
throughput. Single multifunction instructions execute parallel  
ALU and multiplier operations. In SIMD mode, the parallel  
ALU and multiplier operations occur in both processing ele-  
ments. These computation units support IEEE 32-bit single-  
precision floating-point, 40-bit extended precision floating-  
point, and 32-bit fixed-point data formats.  
The ADSP-21364 features an enhanced Harvard architecture in  
which the data memory (DM) bus transfers data and the pro-  
gram memory (PM) bus transfers both instructions and data  
(see Figure 1 on Page 1). With the ADSP-21364’s separate pro-  
gram and data memory buses and on-chip instruction cache,  
the processor can simultaneously fetch four operands (two over  
each data bus) and one instruction (from the cache), all in a sin-  
gle cycle.  
Instruction Cache  
The ADSP-21364 includes an on-chip instruction cache that  
enables three-bus operation for fetching an instruction and four  
data values. The cache is selective—only the instructions whose  
fetches conflict with PM bus data accesses are cached. This  
cache allows full-speed execution of core, looped operations  
such as digital filter multiply-accumulates, and FFT butterfly  
processing.  
Data Register File  
A general-purpose data register file is contained in each  
processing element. The register files transfer data between the  
computation units and the data buses, and store intermediate  
results. These 10-port, 32-register (16 primary, 16 secondary)  
register files, combined with the ADSP-2136x enhanced Har-  
vard architecture, allow unconstrained data flow between  
computation units and internal memory. The registers in PEX  
are referred to as R0–R15 and in PEY as S0–S15.  
Data Address Generators With Zero-Overhead Hardware  
Circular Buffer Support  
The ADSP-21364’s two data address generators (DAGs) are  
used for indirect addressing and implementing circular data  
buffers in hardware. Circular buffers allow efficient program-  
ming of delay lines and other data structures required in digital  
Rev. PrB  
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Page 4 of 52  
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September 2004  
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与ADSP-21364SKBCZENG相关器件

型号 品牌 描述 获取价格 数据表
ADSP-21364SKSQ-ENG ADI SHARC Processor

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ADSP-21364SKSQZENG ADI SHARC Processor

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ADSP-21364WBBCZ-1A ADI SHARC Processor

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ADSP-21364WBSWZ-1A ADI IC 16-BIT, 55.55 MHz, OTHER DSP, PQFP144, MS-026BFB-HD, LQFP-144, Digital Signal Processor

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ADSP-21364WSQZ-2AA ADI IC 16-BIT, OTHER DSP, PQFP144, LEAD FREE, MS-026BFB-HD, LQFP-144, Digital Signal Processor

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ADSP-21364WYSWZ-2A ADI IC 16-BIT, 55.55 MHz, OTHER DSP, PQFP144, MS-026BFB-HD, LQFP-144, Digital Signal Processor

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