ADSP-21364
Preliminary Technical Data
Up to 12 TDM stream support, each with 128 channels per
frame
KEY FEATURES—PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-21364
performs 2 GFLOPS/666 MMACS
3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit
in blocks 2 and 3) for simultaneous access by core proces-
sor and DMA
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
4M bit on-chip, single-ported mask-programmable ROM (2M
bit in block 0 and 2M bit in block 1)
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single-Instruction Multiple-Data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the
SHARC core, configurable as eight channels of serial data
or seven channels of serial data and up to a 20-bit wide
parallel data channel
Signal routing unit provides configurable and flexible con-
nections between all DAI components–six serial ports, two
precision clock generators, an input data port with a data
acquisition port, one SPI port, eight channels of asynchro-
nous sample rate converters, three timers, 10 interrupts,
six flag inputs, six flag outputs, and 20 SRU I/O pins
(DAI_Px)
Two serial peripheral interfaces (SPI): primary on dedicated
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI
Full-duplex operation
Master slave mode multi-master support
Open drain outputs
Programmable baud rates, clock polarities and phases
3 Muxed Flag/IRQ lines
Parallelism in buses and computational units allows single
cycle execution (with or without SIMD) of a multiply or
ALU operation, a dual memory read or write, and an
instruction fetch
Transfers between memory and core at a sustained 5.4
Gbytes/s bandwidth at 333 MHz core instruction rate
1 Muxed Flag/Timer expired line
DEDICATED AUDIO COMPONENTS
S/PDIF compatible digital audio receiver/transmitter
supports:
INPUT/OUTPUT FEATURES
DMA controller supports:
25 DMA channels for transfers between ADSP-21364 internal
memory and a variety of peripherals
32-bit DMA transfers at peripheral clock speed, in parallel
with full-speed processor execution
Asynchronous parallel port provides access to asynchronous
external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I2S or right-justified serial data input with
16-, 18-, 20- or 24-bit word widths (transmitter)
Two channel mode and single channel double frequency
(SCDF) mode
Four independent Asynchronous Sample Rate Converters
(SRC). Each converter has separate serial input and output
ports, a deemphasis filter providing up to -140dB SNR per-
formance, stereo sample rate converter (SRC) and supports
left-justified, I2S, TDM and right-justified modes and 24-,
20-, 18- and 16- audio data word lengths
55 Mbyte per sec transfer rate
External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit packing options
Programmable data cycle duration: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two pre-
cision clock generators, an input data port, three timers,
eight-channel asynchronous sample rate converter, and a
signal routing unit
Six dual data line serial ports that operate at up to 50M bit/s
on each data line—each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair
Pulse-Width Modulation provides:
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in nonpaired mode
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball mini-BGA and 144-lead LQFP Packages
Left-justified sample pair and I2S support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I2S compatible stereo devices per serial
port
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Rev. PrD
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Page 2 of 56
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May 2005
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