PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800/262-5643
April 2002
ADSP-21160N
ADSP-21160N Family Core Architecture
processor that supports 14 DMA channels, two serial ports,
six link ports, external parallel bus, and glueless
multiprocessing.
The ADSP-21160N includes the following archi-
tectural features of the ADSP-2116x family core. The
ADSP-21160N is code compatible at the assembly level
with the ADSP-2106x and ADSP-21161.
The functional block diagram on page 1 shows a block
diagram of the ADSP-21160N, illustrating the following
architectural features:
SIMD Computational Engine
The ADSP-21160N contains two computational process-
ing elements that operate as a Single Instruction Multiple
Data (SIMD) engine. The processing elements are referred
to as PEX and PEY, and each contains an ALU, multiplier,
shifter, and register file. PEX is always active, and PEY may
be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction
isexecutedinbothprocessingelements, buteachprocessing
element operates on different data. This architecture is
efficient at executing math-intensive DSP algorithms.
• Two processing elements, each made up of an ALU, Mul-
tiplier, Shifter, and Data Register File
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycle
• Interval timer
• On-Chip SRAM (4M bits)
• External port that supports:
• Interfacing to off-chip memory peripherals
Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required
to sustain computational operation in the processing
elements. Because of this requirement, entering SIMD
mode also doubles the bandwidth between memory and the
processing elements. When using the DAGs to transfer data
in SIMD mode, two data values are transferred with each
access of memory or the register file.
• Glueless multiprocessing support for six
ADSP-21160N SHARCs
• Host port
• DMA controller
• Serial ports and link ports
• JTAG test access port
Independent, Parallel Computation Units
Figure 1 shows a typical single-processor system. A multi-
processing system appears in Figure 4.
Within each processing element is a set of computational
units. The computational units consist of an arith-
metic/logic unit (ALU), multiplier, and shifter. These units
perform single-cycle instructions. The three units within
each processing element are arranged in parallel, maximiz-
ing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier opera-
tions. In SIMD mode, the parallel ALU and multiplier
operations occur in both processing elements. These com-
putation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point,
and 32-bit fixed-point data formats.
ADSP-21160
CLOCK
CLKIN
CS
BMS
BOOT
EPROM
(OPTIONAL)
4
CLK_CFG3–0
EBOOT
ADDR
DATA
CIF
LBOOT
BRST
3
IRQ2–0
ADDR31–0
ADDR
4
FLAG3–0
TIMEXP
MEMORY/
MAPPED
DEVICES
DATA63–0
DATA
OE
RDx
LINK
DEVICES
(6 MAX)
LXCLK
WE
WRx
ACK
(OPTIONAL)
LXACK
ACK
CS
(OPTIONAL)
LXDAT7–0
MS3–0
Data Register File
TCLK0
RCLK0
TFS0
RSF0
DT0
PAGE
SERIAL
DEVICE
(OPTIONAL)
DMA DEVICE
(OPTIONAL)
A general-purpose data register file is contained in each
processing element. The register files transfer data between
the computation units and the data buses, and store inter-
mediate results. These 10-port, 32-register (16 primary, 16
secondary) register files, combined with the ADSP-2116x
enhanced Harvard architecture, allow unconstrained data
flow between computation units and internal memory. The
registers in PEX are referred to as R0–R15 and in PEY
as S0–S15.
SBTS
DATA
CLKOUT
DMAR1–2
DMAG1–2
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
CS
SERIAL
DEVICE
(OPTIONAL)
HOST
HBR
HBG
PROCESSOR
INTERFACE
(OPTIONAL)
DR1
REDY
BR1–6
PA
RPBA
ID2–0
ADDR
DATA
RESET JTAG
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21160N features an enhanced Harvard archi-
tecture in which the data memory (DM) bus transfers data,
and the program memory (PM) bus transfers both instruc-
tions and data (seethe functionalblock diagram on page 1).
6
Figure 1. Single-Processor System
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrB
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