PRELIMINARY TECHNICAL DATA
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GENERAL DESCRIPTION
April 2002
FEATURES (CONTINUED)
ADSP-21160N
The ADSP-21160N SHARC DSP is the second iteration
of the ADSP-21160. Built in a 0.18 micron CMOS process,
it offers higher performance and lower power consumption
than its predecessor, the ADSP-21160M. Easing portabil-
ity, the ADSP-21160N is application source code
compatible with first generation ADSP-2106x SHARC
DSPs in SISD (Single Instruction, Single Data) mode. To
takeadvantageoftheprocessor’sSIMD(SingleInstruction,
Multiple Data) capability, some code changes are needed.
Like other SHARCs, the ADSP-21160N is a 32-bit
processor that is optimized for high performance DSP appli-
cations. The ADSP-21160N includes an 95 MHz core, a
dual-ported on-chip SRAM, an integrated I/O processor
with multiprocessing support, and multiple internal buses
to eliminate I/O bottlenecks.
Single Instruction Multiple Data (SIMD)
Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—at Assembly Level, Uses the
Same Instruction Set as the ADSP-2106x
SHARC DSPs
Parallelism in Buses and Computational Units Allows:
Single-cycle Execution (with or without SIMD) of: A
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
Transfers Between Memory and Core at up to Four
32-Bit Floating- or Fixed-Point Words per Cycle
Accelerated FFT Butterfly Computation Through a
Multiply with Add and Subtract
4M Bits On-Chip Dual-Ported SRAM for Independent
Access by Core Processor, Host, and DMA
DMA Controller supports:
14 Zero-Overhead DMA Channels for Transfers Between
ADSP-21160N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports, or
Link Ports
The ADSP-21160N introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computa-
tional units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160N can double performance versus the
ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160N has a 10.5 ns instruc-
tion cycle time. With its SIMD computational hardware
running at 95 MHz, the ADSP-21160N can perform 570
million math operations per second.
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
665M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit
Microprocessors
Table 1 shows performance benchmarks for the
ADSP-21160N.
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Generation and Page-Mode for Off-Chip Memory
Multiprocessing Support Provides:
Table 1. ADSP-21160N Benchmarks
Benchmark Algorithm
Speed
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of up to Six ADSP-21160Ns plus Host
Six Link Ports for Point-To-Point Connectivity and Array
Multiprocessing
Serial Ports Provide:
Two 47.5M Bits/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
External Memories
1024 Point Complex FFT (Radix 4, with 96 µs
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
5.25 ns
21 ns
47.25 ns
Matrix Multiply (pipelined)
84 ns
Divide (y/x)
31.5 ns
Inverse Square Root
DMA Transfer Rate
47.25 ns
665M Bytes/s
Thesebenchmarks provide single-channelextrapolationsof
measured dual-channel processing performance. For more
information onbenchmarking andoptimizingDSP codefor
single- and dual-channel processing, see Analog Devices’s
website.
Up to 47.5 MHz Operation
The ADSP-21160N continues SHARC’s industry-leading
standards of integration for DSPs, combining a
high-performance32-bitDSPcorewithintegrated, on-chip
system features. These features include a 4M-bit dual
ported SRAM memory, host processor interface, I/O
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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