ADSP-21xx
ADSP-2111
A13-0
14
BOOT
MEMORY
ADDR13-0
1x CLOCK
or
CRYSTAL
D
CLKIN
ADDR
23-22
(OPTIONAL)
XTAL
e.g. EPROM
D15-8
24
2764
27128
27256
27512
CLKOUT
RESET
DATA23-0
DATA
OE
CS
BMS
IRQ2
BR
A13-0
D23-0
ADDR
DATA
BG
MMAP
PROGRAM
MEMORY
OE
WE
CS
RD
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
WR
(OPTIONAL)
SERIAL
DEVICE
A13-0
D23-8
(OPTIONAL)
ADDR
DATA
DATA
MEMORY
&
SPORT 0
SCLK0
RFS0
TFS0
DT0
PMS
DMS
PERIPHERALS
OE
WE
CS
SERIAL
DEVICE
(OPTIONAL)
(OPTIONAL)
DR0
FL0
FL1
FL2
HOST
PROCESSOR
HOST INTERFACE PORT
CONTROL
7
(OPTIONAL)
16
DATA / ADDR
THE TWO MSBs OF THE DATA BUS (D23-22) ARE USED TO SUPPLY THE TWO MSBs OF THE
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 5. ADSP-2111 System
T he data lines are bidirectional. T he program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. T he write (WR) signal indicates a
write operation and is used as a write strobe. T he read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
T he RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MST AT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). T he first
instruction is then fetched from internal program memory
location 0x0000.
T he ADSP-21xx processors write data from their 16-bit
registers to 24-bit program memory using the PX register to
provide the lower eight bits. When the processor reads 16-bit
data from 24-bit program memory to a 16-bit data register, the
lower eight bits are placed in the PX register.
P r ogr am Mem or y Inter face
T he on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. T he external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
T he program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
P r ogr am Mem or y Maps
T he external address bus is 14 bits wide. For the ADSP-2101,
ADSP-2103, and ADSP-2111, these lines can directly address
up to 16K words, of which 2K are on-chip. For the ADSP-2105
and ADSP-2115, the address lines can directly address up to
15K words, of which 1K is on-chip.
Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 6 shows the two program
memory maps for the ADSP-2101, ADSP-2103, and
ADSP-2111. Figure 8 shows the program memory maps for the
ADSP-2105 and ADSP-2115. Figures 7 and 9 show the
program memory maps for the ADSP-2161/62 and ADSP-2163/
64, respectively.
–10–
REV. B