ADSP-21xx
A clock output signal (CLKOUT ) is generated by the processor,
synchronized to the processor’s internal cycles.
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
Reset
The RESET signal initiates a complete reset of the ADSP-21xx.
T he RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
meet the minimum pulse width specification, tRSP
.
T o generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
Table IV. AD SP -21xx P in D efinitions
P in
Nam e(s)
# of
P ins
Input /
O utput
Function
Address
Data1
14
24
O
I/O
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request # 2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
RESET
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
IRQ2
BR2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XT AL
CLKOUT
VDD
I
O
GND
Ground Pins
SPORT 03
SPORT 1
or Interrupts & Flags:
IRQ0 (RFS1)
IRQ1 (TFS1)
FI (DR1)
FO (DT1)
FL2–0 (ADSP-2111 Only)
5
5
I/O
I/O
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
1
1
1
1
3
I
I
I
O
O
External Interrupt Request # 0
External Interrupt Request # 1
Flag Input Pin
Flag Output Pin
General Purpose Flag Output Pins
Host Interface Port
(ADSP-2111 Only)
HSEL
HACK
1
1
I
O
HIP Select Input
HIP Acknowledge Output
HSIZE
BMODE
HMD0
HMD1
HRD/HRW
HWR/HDS
HD15–0/HAD15-0
HA2/ALE
HA1–0/Unused
1
1
1
1
1
1
16
1
2
I
I
I
I
I
I
8/16-Bit Host Select (0 = 16-Bit, 1 = 8-Bit)
Boot Mode Select (0 = Standard EPROM Booting, 1 = HIP Booting)
Bus Strobe Select (0 = RD/WR, 1 = RW/DS)
HIP Address/Data Mode Select (0 = Separate, 1 = Multiplexed)
HIP Read Strobe or Read/Write Select
HIP Write Strobe or Host Data Strobe Select
HIP Data or HIP Data and Address
I/O
I
I
Host Address 2 Input or Address Latch Enable Input
Host Address 1 and 0 Inputs
NOT ES
1Unused data bus lines may be left floating.
2BR must be tied high (to VDD) if not used.
3ADSP-2105 does not have SPORT 0. (SPORT 0 pins are No Connects on the ADSP-2105.)
–8–
REV. B
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