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ADP3808

更新时间： 2024-01-04 09:58:08
品牌 Logo 应用领域
亚德诺 - ADI 电池开关
页数 文件大小 规格书
16页 339K
描述
High Efficiency Switch Mode Li-Ion Battery Charger

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ADP3808 技术参数

生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN,针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.68
Is Samacsys：N模拟集成电路 - 其他类型：BATTERY CHARGE CONTROLLER
控制技术：PULSE WIDTH MODULATION最大输入电压：22 V
最小输入电压：10 V标称输入电压：20 V
JESD-30 代码：S-XQCC-N24JESD-609代码：e3
长度：4 mm功能数量：1
端子数量：24最高工作温度：100 °C
最低工作温度：封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE认证状态：Not Qualified
座面最大高度：1 mm表面贴装：YES
切换器配置：SINGLE最大切换频率：1000 kHz
温度等级：OTHER端子面层：TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：4 mm
Base Number Matches：1

ADP3808 数据手册

 浏览型号ADP3808的Datasheet PDF文件第3页浏览型号ADP3808的Datasheet PDF文件第4页浏览型号ADP3808的Datasheet PDF文件第5页浏览型号ADP3808的Datasheet PDF文件第7页浏览型号ADP3808的Datasheet PDF文件第8页浏览型号ADP3808的Datasheet PDF文件第9页 
ADP3808  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
ISYS  
LIMSET  
LIMIT  
1
2
3
4
5
6
18 DRVREG  
17 DRVL  
16 PGND  
15 CSP  
ADP3808  
TOP VIEW  
EXTPWR  
RT  
(Not to Scale)  
14 CSM  
REFIN  
13 CSADJ  
Figure 2. LFCSP Pin Configuration  
Table 3. Pin Function Descriptions  
Pin No.  
Mnemonic Description  
1
2
3
4
ISYS  
LIMSET  
LIMIT  
Output for System Current Sense Amplifier.  
System Current Limit Set Point Input.  
System Current Limit Output. This is an open-drain pin and requires a pull-up resistor to a maximum of 6 V.  
External Adapter Sense Open-Drain Output. This pin pulls low when the ac adapter voltage is present. A pull-up  
resistor is required to a maximum of 6 V.  
EXTPWR  
5
RT  
Frequency Setting Resistor Input. An external resistor connected between this pin and AGND sets the oscillator  
frequency of the device.  
6
7
REFIN  
BATADJ  
Reference Input for BATADJ and CSADJ.  
Battery Voltage Adjust Input. This pin uses an analog voltage referenced to REFIN to program voltage from 4.0 V to  
4.5 V per cell.  
8
EN  
Charger Enable Input. Pulling this pin to AGND disables the DRVH and DRVL outputs and puts the circuitry  
powered by VCC into a low power state. The system amplifier and EXTPWR are still active.  
9
COMP  
AGND  
BAT  
CELLSEL  
CSADJ  
Output of Error Amplifiers and Compensation Point.  
Analog Ground. Reference point for the battery sense and all analog functions.  
Battery Sense Input.  
Battery Cell Selection Input. Pulling this pin high selects 3-cell operation; pulling it low selects 4-cell operation.  
Charge Current Programming Input. This pin uses an analog voltage referenced to REFIN to program the battery  
charge current. (VCSP − VCSM) = 96 mV x CSADJ/REFIN.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
CSM  
CSP  
PGND  
DRVL  
DRVREG  
Negative Current Sense Input. This pin connects to the battery side of the battery current sense resistor.  
Positive Current Sense Input. This pin connects to the inductor side of the battery current sense resistor.  
Power Ground. This pin should closely connect to the source of the lower MOSFET.  
Synchronous Rectifier Drive. Output drive for the lower MOSFET.  
Driver Supply Output. A bypass capacitor should be connected from this pin to PGND to provide filtering for the  
low-side supply.  
19  
BST  
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this  
bootstrapped voltage for the high-side MOSFET as it is switched.  
20  
21  
DRVH  
SW  
Main Switch Drive. Output drive for the upper MOSFET.  
Switch Node Input. This pin is connected to the buck-switching node, close to the source of the upper MOSFET,  
and is the floating return for the upper MOSFET drive signal.  
22  
23  
24  
VCC  
SYSM  
SYSP  
Input Supply. This pin does not power the SYS amplifier section.  
Negative System Current Sense Input. This pin connects to the battery side of the system current sense resistor.  
Positive System Current Sense Input. This pin connects to the adapter side of the system current sense resistor.  
This pin also provides power to the system amplifier section.  
25  
Paddle  
This pin should be connected to AGND.  
Rev. 0 | Page 6 of 16  
 
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